標題: 0.5微米高壓元件靜電防護能力改善
Improved the ESD capability of 0.5μm high voltage device
作者: 潘嘉祥
Chia-Hsiang Pan
吳耀銓
Yew-Chuang Sermon Wu
工學院半導體材料與製程設備學程
關鍵字: 靜電放電;ESD
公開日期: 2012
摘要: 在真實世界中,當電子產品遭遇靜電放電現象時可能會故障或是損壞,所以靜電放電現象對於電子產品而言是一個很重要的問題。所有的電子產品在量產前都必須通過靜電放電測試,因此我們需要為每個製程設計靜電放電防護元件或是電路去避免靜電放電測試失效。本論文是討論高壓製程的靜電放電防護元件,這個靜電放電防護元件被驗證在0.5微米高壓製程。在這個高壓製程中高壓對稱NMOS 結構(with NBL)與高壓非對稱NMOS結構(without NBL)可以藉由較大的面積通過靜電放電測試,但是這兩個標準高壓元件具有較高的元件崩潰電壓與導通電壓,其導通電壓分別為80.1V與109.7V,當負的靜電放電電流施加在輸出與輸入級PAD時(ND mode),因為高壓PMOS的崩潰電壓只有62V,將會導致輸出輸入級防護電路受損。 在這個靜電防護案例中,我們不更改製程參數、製程流程與布林運算式,我們修改N-type掩埋的光罩去改善靜電放電能防護力,將N-type掩埋層植入在高壓非對稱NMOS結構下方,結果是,高壓非對稱NMOS 結構(with NBL)的崩潰電壓與導通電壓將降低到60V,因此有N-type掩埋層的高壓非對稱NMOS 結構的靜電防護元件能夠更有效的保護內部電路,此外,在靜電放電現象發生時寄生縱向電晶體可以快速導通去旁通靜電放電電流,一旦縱向電晶體導通,靜電放電電流會遠離元件表面,所以可以在小的佈局面積獲得足夠高的靜電防護能力。
In the real world, electronic product or could malfunction or be damaged when the electronic product to be subjected to Electrostatic Discharge (ESD) event. So the ESD event is an important issue of electronic product. All product must be pass ESD test before mass production. Therefore, we need to design the ESD protection device or circuit to avoid ESD failure for all process. This paper is describe ESD device in high voltage process, This ESD protection device has been verified in 0.5μm high voltage process. In this high voltage process, the standard high voltage symmetric NMOS structure (without NBL) and standard high voltage asymmetric NMOS structure (without NBL) need to depend on large area to bypass ESD current, but both of two standard high voltage devices have higher MOS breakdown voltage and trigger voltage. The trigger voltage of symmetric NMOS structure and asymmetric NMOS structure are 80.1V and 109.7V, respectively. When the I/O PAD is stressed negative current (ND mode), because the breakdown voltage of high voltage PMOS only have 62V, it will cause damage in the I/O cell. In this ESD case, we do not change process parameter, process flow and Boolean operation, we modify the NBL MASK to improved ESD ability, an extra highly dope buried layer implant under the asymmetric NMOS structure, as a result, the breakdown voltage and trigger voltage of asymmetric NMOS will be reduce to 60V, therefore, the asymmetric NMOS with NBL structure can protect internal circuit more effectively. Furthermore, the parasitic VNPN transistor can turn on quickly to bypass ESD current on the ESD event, Once the VNPN transistor turn on, the ESD current can leave the surface of device. So, we can obtain high enough ESD ability in small layout area.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079875518
http://hdl.handle.net/11536/48843
顯示於類別:畢業論文


文件中的檔案:

  1. 551801.pdf