標題: AN EFFICIENT TIMING MODEL FOR CMOS COMBINATIONAL LOGIC GATES
作者: WU, CY
HWANG, JS
CHANG, C
CHANG, CC
電控工程研究所
Institute of Electrical and Control Engineering
公開日期: 1985
URI: http://hdl.handle.net/11536/4823
ISSN: 0278-0070
期刊: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume: 4
Issue: 4
起始頁: 636
結束頁: 650
顯示於類別:期刊論文


文件中的檔案:

  1. A1985AUB1500033.pdf