標題: 擁有寬捕獲範圍之全數位鎖相迴路電路設計
A Wide Capture Range PLL based on All-Digital Design
作者: 謝進益
Hsieh, Chin-Yi
高銘盛
Kao, Ming-Seng
電信工程研究所
關鍵字: 鎖相迴路;全數位鎖相迴路;捕獲範圍;Phase-Locked Loop;PLL;ADPLL;Capture Range
公開日期: 2010
摘要: 本論文設計一個擁有極寬捕捉頻帶的全數位鎖相迴路,其鎖定頻率範圍從1kHz到1MHz。此鎖相迴路的最高頻率與最低頻率的倍率為1000,並且使用者不需知道輸入頻率的範圍,只要工作頻率位於此區間的應用,皆可使用此電路。為了能夠適用於充滿雜訊的環境,所設計的電路擁有良好的抗雜訊能力,即使在SNR=0dB的惡劣環境中,它依然可以正常的運作。在設計時,我們著重於三個效能參數: 頻率鎖定的正確率、鎖定效率與抗頻率漂移能力。為了能在各個面向都有良好的表現,我們設計三種不同的工作模式及對應的演算法,其中包含捕獲模式、追蹤模式與相位修正模式,並且在實際電路中選擇使用雙迴路的方式,以完成一個全數位雙迴路鎖相電路。最後,我們利用硬體描述語言實現此鎖相迴路,以驗證其可行性。
In this thesis we design an all-digital phase-locked loop (PLL) with ultra-wide capture range which spans from 1kHz to 1MHz. The ratio of the highest frequency to the lowest frequency is 1000 and there is no need for prior information of the input frequency. With this PLL, all applications whose working frequency is within this frequency range could use it to implement the corresponding system. Also, for applying it in noisy environment, the PLL is asked to have good noise immunity. It is designed to work efficiently when SNR=0dB. On designing this PLL, we focus on three aspects: the frequency locked rate, the lock efficiency and the capability of anti-frequency drift. For good efficiency in every aspect within wide capture range under noisy environment, we design three different states which include the acquisition state, the tracking state and the phase-fixing state. Moreover, we introduce the dual-loop system to further improve the performance. Finally, to verify the feasibility of our approach, we implement this PLL by Hardware Description Language based on all-digital design.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079813569
http://hdl.handle.net/11536/47051
Appears in Collections:Thesis


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