Title: 一個具備數位背景式校正機制之十三位元每秒一億次取樣0.18-um CMOS導管式類比數位轉換器的設計
Design of a 13-bit 100-MS/s Pipelined ADC with Digital Background Calibration in 0.18-um CMOS
Authors: 劉議煌
Liu, Yi-Huang
Hong, Hao-Chiao
Keywords: 導管式類比數位轉換器;數位背景式校正;Pipelined ADC;Digital background calibration
Issue Date: 2011
Abstract: 傳統pipelined ADC的設計中在最前端的multiplying digital-to-analog conve- rter (MDAC)電路必須符合最嚴格的雜訊、速度及線性度規格,因此需要一個開迴路增益很高、單增益頻寬很大的運算放大器。此放大器因而消耗了整個ADC大部分的功率。另外,隨著製程不斷地演進,供應電壓的下降限制了訊號的輸出擺幅,電晶體的通道長度縮小也降低其本質增益,造成使用先進製程來設計出具有高增益及高頻寬的運算放大器變得非常困難。 為了大幅降低功率消耗,並且降低在先進製程下的設計難度,本論文提出一個具備數位背景式校正機制之十三位元、每秒一億次取樣pipelined ADC的設計。本設計在pipelined ADC規格需求最高的第一級使用一個架構非常簡單的開迴路式殘值放大器來取代傳統功率消耗非常大的閉迴路式架構。因開迴路式電路而產生的增益誤差及三階非線性誤差,則透過一個數位背景式校正機制來估測誤差量且即時將錯誤校正。在先進製程下,利用數位輔助類比電路設計的概念,實現一個高效能的pipelined ADC。 本論文設計之pipelined ADC使用TSMC 0.18-um CMOS製程實現,而數位校正的部分則以FPGA實現。最後,將測試晶片與FPGA整合以量測此ADC校正後之效能。量測結果顯示,在類比電路的供應電壓為1.65V、數位電路的供應電壓為1.8V且取樣頻率為12MS/s的情況下,校正前ADC的有效位元為5.3 bits,而校正後可以被改善至7.2 bits。限制此實作晶片校正後之效能的可能原因有二。首先,由於校正級與backend stage第一級中sub-ADC的比較器觸發時序設計錯誤,導致此ADC無法正常運作且無法對backend stage的偏移誤差進行補償。第二,FPGA板上的flash memory限制了此ADC只能操作在12MS/s的取樣頻率。
In the front-end of a conventional pipelined ADC, the embedded multiplying digital-to-analog converter (MDAC) has to meet very stringent noise, speed, and linearity requirements. As a result, the MDAC needs an operational amplifier (OP) with a very high open-loop gain and a large unity-gain bandwidth. Such an OP dominates the overall power dissipation of the pipelined ADC. Moreover, as the advanced technology keeps scaling, the reduced supply voltage limits the signal headroom and the reduced channel length decreases the intrinsic gain of transistors.Consequently, it is very difficult to design an OP that can achieve the stringent specifications with the advanced technology. In order to save power and alleviate the design difficulty in advanced technology,this thesis proposes a 13-bit 100-MS/s pipelined ADC with digital background calibration. The design replaces the conventional closed-loop residue amplifier with a simple open-loop architecture in the first pipelined stage which specifications is the most stringent in the pipelined ADC. The gain error and the third-order nonlinearity of the open-loop residue amplifier are calibrated using a digital background calibration technique. The calibration scheme continuously estimates and calibrates the errors introduced by the imprecise and nonlinear gain of the open-loop residue amplifier. By adopting the concept of digital-assist analog circuit design, this thesis implements a high performance pipelined ADC with the aid of CMOS scaling. The proposed pipelined ADC has been designed and fabricated in a TSMC 0.18-um CMOS process and the digital background calibration is implemented by a FPGA. The measurement results show that the ENOBs of the ADC output with calibration and without calibration at an analog power supply of 1.65V, a digital power supply of 1.8V, and a sampling rate of 12MS/s are 5.3 bits and 7.2 bits,respectively. There are two possible reasons that cause the performance degradation of the pipelined ADC. First, the pipelined ADC can’t work properly and the offset of the backend stage can’t be cancelled because of a timing error of the comparator design. Second, the operating speed of the flash memory on the FPGA board limits the sampling rate of the pipelined ADC to be less than 12MS/s.
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