標題: 藉由擁擠感知區塊移動佈局之三維積體電路直通矽穿孔規劃演算法Efficient TSV Planning Algorithm via Congestion-Aware Block Shifting in 3D Floorplanning 作者: 黃崇羽Huang Chung-Yu黃俊達Huang Juinn-Dar電子研究所 關鍵字: 佈局;直通矽穿孔;三維積體電路;floorplan;TSV;3D IC 公開日期: 2011 摘要: 隨著積體電路的發展，近年來三維積體電路被提出。相較於二維積體電路，三維積體電路把多個晶粒(die)堆疊成立體的結構，並且利用直通矽穿孔(through-silicon vias, TSVs) 傳遞層與層之間的信號，此種結構提供了改善積體電路效能的可能性。 在此種結構下，必須要考慮直通矽穿孔在佈局(floorplan)上所擺放的位置，由於直通矽穿孔用來傳遞層與層之間的信號，故其擺放位置的好壞會決定電路的線長與效能。為此，我們在這篇論文提出一個適用於三維積體電路佈局上的直通矽穿孔規畫的演算法─CABS，藉由擁擠感知(congestion-aware)來移動區塊(block shifting)並且規劃直通矽穿孔的位置。首先在佈局上計算所需要直通矽穿孔的程度藉以得知在佈局上不同區域直通矽穿孔需求擁擠的情況。接者我們會在擁擠程度高的區域來放置直通矽穿孔區塊(TSV bins)；直通矽穿孔區塊是一個區塊視為數個直通矽穿孔的集合，直通矽穿孔皆須擺在直通矽穿孔區塊裡面。最後我們利用最短路徑演算法來指定直通矽穿孔到直通矽穿孔區塊。實驗結果顯示，相較於前人的演算法，我們不僅在執行時間和直通矽穿孔的數量上有大幅的領先，在線長(wirelength)方面也有11%的改善。此一方法在給定的初始電路佈局下，能夠在不大幅影響初始結果下很快速的規劃矽穿孔的位置，並達成線長及面積的最佳化。With the development of integration technology, 3D integrated technology has been proposed in recent years. Compared to the 2D integration technology, 3D integration technology stacks multiple dies to form a 3D structure and the through-silicon vias (TSVs) are utilized for signals transmission between layers. The 3D structure provides a good opportunity for improving system performance. In this unique structure, we must consider the positions of TSVs in a floorplan. Because the area of through-silicon vias (TSVs) is significant and cannot be ignored, the result of TSV planning has a great impact on the quality of design in terms of wirelength and performance. Therefore, in this thesis, we propose a TSV planning algorithm via congestion-aware block shifting (CABS) in 3D floorplanning. First, we identify net-congestion regions in a floorplan. Then we allocate TSV bins for those net-congestion regions, where a TSV bin can be used to place a set of TSVs. After allocating TSV bins, every TSV has to be bound to one of those TSV bins. We model the TSV binding problem as a shortest-path problem wirelength minimization. Experimental results show that we achieve not only significant reductions in both the number of TSVs and runtime but also 11% improvement in wirelength as compared with the prior art. Through a series of minor changes in an initial floorplan, our algorithm can perform TSV planning extremely fast and produce excellent results of wirelength and area minimization. URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079811685http://hdl.handle.net/11536/46850 顯示於類別： 畢業論文