標題: 使用0.25μm CMOS技術製作的一個完全積體化共模三頻帶低雜訊放大器及兩個改良型混頻器電路設計
The Design of A Fully Integrated Concurrent Triple-Band LNA and Two Modified Mixer Circuits Fabricated using 0.25um CMOS Technology
作者: 呂盈蒼
Ying-Tsang Lu
周復芳
Dr. Christina F. Jou
電信工程研究所
關鍵字: 三頻帶低雜訊放大器;整合型混頻器;微混頻器;互補式金氧半技術;射頻積體電路;共模低雜訊放大器;triple-band LNA;merged mixer;micromixer;CMOS;RF IC;concurrent LNA
公開日期: 2003
摘要: 在此篇論文研究中,主要探討三個主題;第一個主題是設計一個完全積體化共模三頻帶CMOS低雜訊放大器,它的設計理念是來自原本的共模雙頻帶低雜訊放大器,輸入及輸出匹配電路經過改良設計後,可提供在所希望的三個頻段(1.8GHz, 2.45GHz, 5.25GHz)相當好的匹配,結合偏壓電流重新利用技巧的雙級架構,可用來同時達到較高的增益,卻不需大量的功率損耗,除此之外,此電路亦在這三個不同頻率呈現出相當高的線性度;最後,經由模擬及量測結果中,我們驗證了這個設計理念的可行性,並探討其間的差異性。第二個主題是設計一個操作在2.1GHz整合低雜訊放大器的雙平衡混頻器電路,此電路架構是將低雜訊放大器和混頻器以電流模式串疊起來,因此可以消去傳統以電壓模式串疊架構之中間節點,並去除相關之線性度瓶頸;此外,此電路亦包含兩種改良機制,第一,加入一對共閘NMOS電晶體於共源低雜訊放大器及切換混頻對尾端之間,以提昇LO至RF之隔絕度,第二,加入一對共源PMOS電晶體同時扮演除了可改善線性度、增益及降降雜訊指數之分流源外,也可透過兩個耦合電容來作小訊號共源放大器以提昇增益;同樣的,經由模擬及量測結果中,我們亦驗證了這個設計改良的理念。最後一個主題是設計一個全新的CMOS微混頻器,它的設計理念是源自目前的BJT微混頻器,一般來說,因為成效不佳的關係,此電路架構並不適合應用在CMOS上,但經過改良設計後之新架構,不但可達到相當不錯的成效,且所損耗的功率亦非常低,在新架構中,除了加入一對LC tank及一對耦合電容外,亦增加了一對NMOS電晶體,它可同時用來當作改善線性度、增益和降低雜訊指數之分流源以及可提昇增益之高頻電流放大器,最後,我們亦經由模擬及量測結果中驗證了這個設計改良的理念。以上三組電路皆巳透過CIC於台積電以0.25μm CMOS技術實現及製作出來,並皆巳完成各電路所有參數量測工作,在此篇論文中,我們會在每一個電路設計之最後,針對量測及模擬結果做進一步的比較和討論。
This thesis contents three works. First, we design a novel fully integrated concurrent triple-band CMOS LNA. The design idea originates from the concurrent dual-band LNA. The input and output matching circuits have been modified to provide good matching at all desired triple bands (1.8GHz, 2.45GHz, and 5.25GHz). A two-stage topology conjunction with bias-current reuse technique has been used to simultaneously achieve high gain without large amount of power consumption. Besides, it also exhibits high linearity at these three different frequencies. Finally, we have demonstrated this design idea through post simulation and measurement results and discuss the differences between them. The second work is the design of a modified double-balanced mixer merged LNA which can be operated at 2.1GHz. This architecture is a current-mode cascade of LNA and mixer, so that it can eliminate the intermediate node of the conventional voltage-mode cascade architecture and remove the associated bottleneck to linearity. Besides, two kinds of improving mechanisms are included in this circuit. First, a pair of common-gate NMOS transistors is added between common-source LNA and the tail of commutating mixer pair to improve LO-to-RF Isolation. Second, a pair of PMOS transistors is added to simultaneously act as not only bleeding-current sources to improve linearity, gain, and noise figure but also small signal common-source amplifiers to achieve higher gain through two coupling capacitors. Similarly, we have demonstrated this design idea through post simulation and measurement results. The last work is the design of a new CMOS RF MICROMIXER. The design idea originates from the current BJT counterpart. In general, this topology is unsuited for CMOS applications due to worse performance. But the new topology modified here can achieve better performance with very low power dissipation. In addition to LC tank pair and coupling capacitor pair, a pair of NMOS transistors is also added in the new architecture that can be used as not only bleeding-current sources to improve linearity, gain, and noise figure but high frequency current amplifiers to increase gain. Finally, we also have demonstrated this design idea through post simulation and measurement results. These circuits all have been implemented and fabricated using TSMC 0.25μm CMOS technology through CIC. And then we have completed all parameter measurements for each work. Throughout this thesis, we will make advanced comparison and discussion between measurement and simulation results in the end of each circuit design.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009113597
http://hdl.handle.net/11536/46846
Appears in Collections:Thesis


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