標題: 藉由更改電路佈局來增加聚焦離子束對訊號的探測能力與修正電路之能力
Design-for-Debug Layout Adjustment for FIB Probing and Circuit Editing
作者: 陳擴安
Chen, Kuo-An
趙家佐
Chao, Chia-Tso
電子研究所
關鍵字: 聚焦離子束;訊號探測力;修正電路;Design-for-Debug;DfD;FIB Probing;Circuit Editing
公開日期: 2010
摘要: 在製程技術快速的演進之下,聚焦離子束的解析度卻無法達到相同速度的發展。因此,對於先進製程來說,當運行在除錯程序下可藉由聚焦離子束來觀察到的訊號數量就大幅減少。這篇論文提出了一個修正電路佈局的架構,經由一些更改電路佈局的動作來達到增加聚焦離子束所能觀察的訊號數量,甚至更進一步能夠達到增加修正電路的機會。所有更改電路的動作都有遵循設計法則,並且不需要重新對整個電路核心進行重新繞線,也因此能夠輕易地與任何商用繞線軟體進行整合。整體實驗是運行在90奈米製程技術下,實驗結果證明了這篇論文所提出的方法能夠在維持原來電路的效能之下,有效地增加聚焦離子束所能觀察到的訊號數量以及增加修正電路的可能性。
While the technology node continually and aggressively scales, the resolution of FIB techniques does not scale as fast. Thus, the percentage of nets which can be observed or repaired through FIB probing or circuit editing is significantly decreased for advanced process technologies, which limits the candidates that can be physically examined through the FIB techniques during the debugging process. This thesis introduces a design-for-debug framework which can adjust the layout to increase the FIB observable rate and the FIB repairable rate for its signals. The layout adjustment is made through pre-defined simple operations subject to the design rules and the timing constraints. Hence, the proposed framework does not require a complicated router as its core and can be applied in conjunction with any commercial APR tool. The experimental result based on the 90nm technology has demonstrated that the proposed DFD framework can effectively increase the FIB observable and repairable rates under different parameter settings while the overall area and circuit performance remain the same.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079811680
http://hdl.handle.net/11536/46844
Appears in Collections:Thesis


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