Title: 一個具有干擾排除能力且應用於無線區域網路的低雜訊放大器
An Interference-Rejecting Low Noise Amplifier for WLAN Application
Authors: 江品全
Keywords: 低雜訊放大器;無線區域網路;干擾;LNA;WLAN;Blocker
Issue Date: 2011
Abstract: 在現代射頻接收器的架構中,吾人通常需要安置一個帶通濾波器於低雜訊放大器之前。在許多應用下,接收器皆必須滿足由各種頻率及其對應強度所組成的干擾訊號模板,當然在無線區域網路之應用亦不例外。 本論文提出了一個創新的低雜訊放大器架構,其特色是具有干擾排除能力。我們亦發展了一個新的帶拒濾波器之設計方法,藉由雙線性轉換,設計者可有系統地得到所要的頻寬且可應用此法於任何頻率之系統。吾人期待日後以此架構為基準的射頻接收器能達到不須前置表面聲波濾波器之最終目標。此電路使用台積電 0.18微米 CMOS製程,由量測結果得知,當操作電壓為1.8V 時,核心電路的直流消耗功率為21.58mW,電壓增益為24.79dB,雜訊指數為5.47dB,單位增益壓縮點及輸入端三階交互調變交叉點分別為-21dBm及-13.5dBm。
In the modern RF (Radio frequency) receiver structures we often place a surface acoustic wave (SAW) filter before the low-noise amplifier (LNA). In many applications, including the wireless local area network (WLAN), a receiver must satisfies the blocking template which denotes the frequencies and corresponding power of the interferences. This thesis reveals a novel structure of an interference-rejecting low noise amplifier. We also developed a novel design methodology of notch filters. By using the bilinear transformation, designers can apply this theorem to obtain the desired bandwidth for any interested frequency range. For those receivers based on this structure, the ultimate goal, i.e. the SAW-Less front-end can be expected. This work is fabricated by using TSMC 0.18-μm CMOS process. From the measurement results, this work consumes 21.58mW DC power under a 1.8-V supply voltage. The voltage gain, noise figure (NF), 1-dB compression point (P1dB) and input-referred third-order intermodulation point (IIP3) is 24.79dB, 5.47dB, -21dBm and -13.5dBm, respectively.
Appears in Collections:Thesis