Title: 40奈米1.0Mb 6T管線化靜態隨機存取記憶體與步階升壓型字元線和適應性數據感知寫入輔助設計
40nm 1.0Mb 6T Pipeline SRAM with Step-Up Word- Line and Adaptive-Data-Aware Write-Assist Design
Authors: 張琦昕
Chang, chi-Shin
Chuang, Ching-Te
Keywords: 靜態隨機存取記憶體;SRAM
Issue Date: 2011
Abstract: 越來越多的記憶體被使用在今天的電子產品,因此設計記憶體變得至關重要。靜態隨機存取記憶體常用於高性能微處理器緩存和嵌入式系統應用,因為它具有最高的運行速度比其他記憶體系列。傳統的6T 靜態隨機存取記憶體使用“thincell”佈局,以實現高密度,因此它成為靜態隨機存取記憶體設計的主流。然而,隨著最近CMOS技術縮放,實現高良率最大的障礙是製程變化。製程變化對於6T 靜態隨機存取記憶體而言特別的嚴重因為小元件尺寸和大容量。在先進技術節點這將嚴重降低了靜態隨機存取記憶體單元的操作區間。在低電壓操作,傳統的6T 靜態隨機存取記憶體幾乎是不可能存活的。 對於 6T 靜態隨機存取記憶體在先進過程,為了提升生存的可能性,我們提出了讀/寫輔助電路技術。被提出的步階升壓型字元線技術提高讀取的雜訊限度伴隨著可接受損失的讀取速度和寫入雜訊限度。寫入能力和寫入性能藉由行基礎的適應性數據感知寫入輔助設計來提升。我們還使用管線化技巧去提高運行速度。在這項工作中,我們實現了一個 1.0Mb高性能6T 靜態隨機存取記憶體,帶有 2個階段管線化與單電源電壓在40奈米低待機功耗大容量互補金屬氧化物半導體技術。該晶片可以工作在寬電壓範圍從 1.2V至0.7V,具有工作平率800MHz@1.2V 和 25oC。
More and more memory is used in today’s electronic products, and consequently the design of memory is becoming crucial. SRAM is usually used in high-performance microprocessor cache and embedded system applications because it has highest operating speed than other memory family. Conventional 6T SRAM use “thincell” layout to achieve high density, so it becomes the mainstream of SRAM design. However, with recently CMOS technology scaling, the greatest barrier to achieving high yield is process variation. The process variation is especially serious for high density SRAM because of the small device size and large capacity. This will seriously degrade the SRAM cell operating margin in advanced technology node. In the low-voltage operation, the conventional 6T SRAM is almost impossible to survive. For the 6T SRAM in the advanced process, in order to promote the survival probability, we proposed Read/Write assist circuit techniques. The proposed Step-Up Word-Line technique improves Read Static Noise Margin with acceptably loss of read speed and Write margin. The Write ability and Write performance are enhanced by a column based Adaptive-Data-Aware Write-Assist scheme. We also use Pipeline scheme to increase the operating speed. In this work, we implement a 1.0Mb high-performance 6T SRAM with 2 stages Pipeline with a single supply voltage in the 40nm Low-Standby-Power bulk complementary metal-oxide semiconductor technology. The chip can operate across wide voltage range from 1.2V to 0.7V, with operating frequency of 800MHz@1.2V and 25oC.
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