標題: G.SHDSL之可適應性等化器及格狀編碼解碼器的硬體設計
Hardware Architecture Design of Adaptive Equalizer and TCM Decoder
作者: 李佳勳
紀翔峰
電信工程研究所
關鍵字: 格狀編碼解碼器;TCM decoder;THP
公開日期: 2004
摘要: 單銅絞線高速數位用戶迴路 (Single-pair High Speed Digital Subscriber Loop,SHDSL),為新一代的對稱式DSL技術。可提供對稱的上下傳速率,最高可達2.3Mbps。然而,在通訊系統中常見的ISI (InterSymbol Interference)問題,同樣的在SHDSL系統中也會遇到,為了使傳輸效能不受ISI影響,我們必須設計一個可適應性的等化器解決ISI問題。常用的決策回授等化器有錯誤蔓延等的缺點存在,且不容易加上TCM解碼器以增加通道編碼增益。我們想要一個可以解決ISI問題同時容易得到通道編碼增益的等化器,而Tomlinson-Harashima precoder(THP)系統有這項優點。所以我們以G.SHDSL規範,針對THP系統與TCM解碼,從演算法設計及電腦模擬開始,最後設計出符合成本效益之硬體架構,所得到的硬體以50MHz的操作頻率即可以符合最大傳輸速率的條件,同時以FPGA模擬板驗證了硬體功能。
The Single-pair High Speed Digital Subscriber Loop (SHDSL) is the new generation symmetric DSL technique which could supply at most 2.3 Mbps downlink and uplink data rate symmetrically to subscribers on a long loop. However, the InterSymbol Interference (ISI) is severe especially duration the transmission over a long loop. Normal data transmission is impossible without properly taking care of the ISI problem. To assure SHDSL tranceivers to provide full-rate transmission, we need a powerful adaptive equalizer to ease the ISI problem. The decision feedback equalizer is the most often used equalizer for sovling the ISI problem. However, it has the error propagation problem, which will degrade the system performance. To improve the performance, the joint equalization and channel decoding is necessary. Nevertheless, combining the trellis decoder in the decision feedback equalizer will result in high complexity hardware. A powerful equalizer called Tomlinson-Harashima precoder (THP) system was proposed to solve this problem. By use of the procoding technique, the joint equalization and channel decoding can be accomplished by cascade a linear equalizaer and a TCM decoder for channel coding. In this theisis, starting from algorithm design and computer simulation, we design the THP system and TCM decoder hardware architectures according to the G.SHDSL recommendation. The resulting hardware could achieve the maximum 2.3 Mbps data rate under the 50 MHz operation clock. The hardware was verified on the FPGA development board.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009113570
http://hdl.handle.net/11536/46568
Appears in Collections:Thesis


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