標題: 應用於平台式晶片系統之溫度認知功率管理的軟體矽智財設計
A Thermal-Aware Power Management Soft-IP for Platform-based SoC Designs
作者: 詹謹鴻
闕河鳴
電信工程研究所
關鍵字: 晶片系統;平台式;軟體矽智財;功率管理;soc;platform-based;soft IP;power management
公開日期: 2003
摘要: 基於目前平台式晶片系統設計(Platform-Based SoC Design)的概念,提出一個溫度認知功率管理的軟體矽智財設計(Thermal-Aware Power Management Soft-IP Design)。此外,另提出了一個溫度認知功率管理裝置的系統層級架構,包括了功率管理匯流排,此溫度認知功率管理裝置與其介面電路;形成一個軟體矽智財。利用此設計,對於晶片系統提供了更穩定的功率與溫度監控且增加了系統效能,並對指定的狀況做出立即的反應,進而使用不同的控制機制來調變功率及溫度去達到指定的限制範圍。只要使用少許系統的資源與硬體的需求,就能彈性的支援不同的功率和溫度的管理,提供一個完善的即時管理方法。此相關模組設計使用TSMC 0.25um 1P5M CMOS製程參數,經過完整的功能驗證後,通過台灣國家晶片中心[1]的審查,由台灣積體電路公司製造。完整的晶片量測在本實驗室完成,使得成果成為一個準軟體矽智財(Prototype Soft-IP)。
A novel thermal-aware power management (TAPM) Software Intellectual Property (Soft-IP) for modern platform-based SoC designs is presented in this thesis. This research proposes a system-level architecture of thermal-aware power management, which includes a Power Management Bus (PMB), TAPM Soft-IP and interface circuitry for proposed PMB. Each component of proposed design is encapsulated to a Soft-IP. With above design, system architects are able to incorporate on-chip power-controls and sensors to achieve nominal power dissipation and ensure the targeting system working within specification. The design yields intricate control and optimal management with little system overhead and minimum hardware requirements, as well as provides the flexibility to support different management schemes. The proposed system and its components are designed, implemented and verified by a prototype chip, which was fabricated in a TSMC 0.25um 1P5M standard CMOS technology through Chip Implementation Center (CIC), Taiwan [1].
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009113567
http://hdl.handle.net/11536/46534
Appears in Collections:Thesis


Files in This Item:

  1. 356701.pdf
  2. 356702.pdf