標題: MISO W-CDMA高速下鏈收發機之軟體與硬體實現
Software and Hardware Realization of MISO W-CDMA High Speed Downlink Transceiver
作者: 李韋琦
Wei-Chi Lee
李大嵩
Ta-Sung Lee
電信工程研究所
關鍵字: 智慧型天線;空時編碼技術;smart antenna;space-time coding
公開日期: 2003
摘要: 由於近年來無線通訊技術的迅速發展,頻譜已成為日益寶貴之資源。因此,第三世代(3rd Generation, 3G)及下一世代(Beyond 3rd Generation, B3G)之無線通訊技術的重要課題即為能有效地提昇頻譜使用效率,並且利用數位訊號處理的方式來改善無線接取的技術,以提昇通訊系統的品質及容量。在3G及B3G的系統中,智慧型天線通訊技術為極具代表性之研究主題,係因其可於不需增加頻寬的前題下,有效降低干擾量,從而使傳輸容量有效增加;同時並提供了空間分集效益以克服通道衰減等問題,並增加接收訊號的品質及可靠度。在本論文中,吾人採用Aptix® MP3C為發展平台;藉由平台上之FPGA及DSP等可程式化組件,來實現MISO W-CDMA高速下鏈收發機的軟硬體架構。其中,FPGA為可程式化之邏輯元件,利用硬體描述語言合成數位邏輯電路,具有可重構性之特性,提供快速之硬體驗證。而DSP則擁有高速之浮點或定點運算,可用以實現即時的訊號處理。系統中包括有時序同步電路、展頻╱解展頻電路、空-時區塊編碼╱解碼電路、自動頻率控制器,以及迴旋編碼╱解碼電路完成系統基頻部分的電路實現,並結合實際量測之通道,以增加系統的正確性與可靠度。最後,吾人進一步導入軟體無線電之概念,透過DSP程式之參數控制及FPGA硬體電路的模組化,以增加系統之擴充性及可適性。
With the growing of wireless communication technologies in recent years, the spectral spectrum has become an increasingly precious source. Therefore, a major issue of wireless communication technologies in the 3G (3rd Generation) and B3G (Beyond 3rd Generation) systems is to enhance the quality and capacity of communication systems. In particular, spectral efficiency must be effectively increased, while radio access technique can be improved via digital signal processing. In the 3G and B3G systems, the smart antenna technique is one of the most representative research topics. Without increasing the bandwidth, a smart antenna boosts transmission capacity through suppressing interferences. On the other hand, it also provides spatial diversity to mitigate channel fading problems and enhance signal quality and reliability. In this thesis, we adopt the Aptix® MP3C as our development platform, and realize software and hardware architectures of an MISO W-CDMA high speed downlink transceiver via of programmable FPGAs and DSPs on the platform. FPGA is a programmable logic device which can be used to design digital logic circuits by hardware description language and can provide fast hardware verification based on its reconfigurability. On the other hand, DSP is a powerful processor with high speed floating-point or fixed-point operations, which is suitable for real-time signal processing. The developed system includes a time synchronizer, a spread/ despread circuit, a space-time block encoder/ decoder circuit, an auto frequency controller, and a convolution encoder/ decoder circuit, giving a complete baseband circuit. Combining the baseband circuit with real measured channel data, we could increase the accuracy and reliability of the system. Finally, we introduce the concept of software-defined radio, with which the scalability and adaptivity of the system could be improved by parameter control of DSP programs and modulizing hardware circuits of the FPGA.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009113552
http://hdl.handle.net/11536/46401
Appears in Collections:Thesis


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