標題: 適用於H.264/AVC之降低記憶體頻寬的動作補償
A Memory Bandwidth-Reduction Motion Compensator for H.264/AVC Application
作者: 陳浩民
Chen, Hao-Min
李鎮宜
Lee, Chen-Yi
電機學院電子與光電學程
關鍵字: 解碼器;動作補償;記憶體;頻寬;H.264;decoder;Motion Compensation;memory bandwidth;High Profile
公開日期: 2010
摘要: 近年來,對於已被數位視訊廣播的高傳真電視廣播服務和藍光光碟所採用的H.264/AVC High Profile視訊標準,其需求是很必要的。而動作補償單元的計算量通常占了整個視訊解碼系統的大多數,這是由於它需要對參考畫面的記憶體有相當大量的資料傳輸。特別在目前最先進的 H.264/ AVC Main/High Profile視訊標準支援了雙向參考畫面,因而使得所需的記憶體頻寬大量增加。我們提出的記憶體頻寬縮減策略除了可有效地減少所需的記憶體頻寬高達80 %之外,同時維持和整個視訊解碼系統相同的解碼順序。和傳統的架構相較之下,針對 H.264 提出的可重新架構的內插器,可省下 20 % 的邏輯閘數量。我們的動作補償單元同時支援了 H.264 Baseline Profile @ 4.0 Level 和 H.264 Main/High Profile @ 4.0 Level,對即時解碼能力而言可達到 1080 HD @ 100.0 MHz,而總邏輯閘數量為 68 K。
In recent years, H.264/AVC High Profile video standard, which has been adopted by the Digital Video Broadcasting (DVB) HDTV broadcast service and the Blu-ray Disc storage format, is necessary in demand. The computation time of motion compensation unit is usually accounted for most of the video decoding system because of the enormous data transfer with reference frame memories. Particularly in the most advanced H.264/AVC Main/High Profile video standard supports bi-prediction reference frame, which makes the memory bandwidth required for a significant increase. Our proposed reduction strategies of memory bandwidth cannot only effectively reduce the required memory bandwidth up to 80% but also maintaining the same decoding order as that of entire video decoding system. The proposed restructured interpolator can save 20% of the number of logic gates compared to traditional design. Our motion compensator also support H.264 Baseline Profile @ 4.0 Level and Main/High Profile @ 4.0 Level, in terms of real-time decoding up to 1080 HD @ 100 MHz, while the total number of 68k NAND2 CMOS logic gate count.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079767506
http://hdl.handle.net/11536/46295
Appears in Collections:Thesis


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  1. 750601.pdf