On Exploration and Simulation for the Placement of Inter-Stratum Thermal Pad and Thermal Through Silicon Via in 3-D IC
|關鍵字:||三維積體電路;熱矽穿孔;層間散熱片;熱消散;3D ICs;thermal through silicon via;inter-stratum thermal pad;thermal dissipation|
|摘要:||隨著移動式產品已逐漸成為消費性電子產品的一大主流，我們清楚的知道移動式產品正朝向小型化、高效能、多功能、低耗能與低成本的趨勢前進。將不同功能與不同製程世代 IC 堆疊起來的3D ICs，對於幫助維持消費者對電子產品尺寸、效能、功能和節能需要的增加而言，無疑是一個重要且可行的解決方案。
相較於2D ICs，3D ICs雖然具有眾多的優點。然而，由於為數不少的介電層所累積絕熱的效應以及功率密度的快速增加，導致3D ICs的溫度較2D ICs高出許多。這也使得熱消散相較於2D ICs而言，更成為3D ICs的嚴峻挑戰。
With mobile products, in which we clearly know that there is a growing trend toward miniaturization, high-performance, multi-function, low-energy and low-cost, have become one of the mainstreams of consumer electronic products. We have no doubt, it is important and feasible solution to stack above different function and different generation integrated circuits together by the three- dimensional integrated circuits ( 3D ICs) in helping maintain the increasing consumer demand for electronic products on scaling, performance, function, and economy. Although 3D ICs have a number of advantages over traditional two-dimensional integrated circuits (2D ICs), the maximum temperature of 3D ICs is still much higher than that of 2D ICs due to insulating effects from numerous dielectric layers and increasing rapidly power densities. Hence, thermal dissipation has become a more serious challenge in 3D ICs than in 2D ICs. In this thesis, we proposed a novel scheme which not only effectively integrate both the white spaces and thermal through silicon vias (TSVs) which correspond to the lower stratus of hot zone, but also create and insert a rectangular shape, called Inter-Stratum Thermal Pad (ISTP), into the adhesive bonding layer for improving its heat conduction, reducing the thermal dissipation problems of 3D ICs. Through a series of simulation, compared to original structure, our novel scheme can reduce the maximum temperature of hot zone more than 15%.
|Appears in Collections:||Thesis|