標題: 非同步雙道超大指令字組處理器之指令壓縮設計
Instruction Compression Design for Asynchronous two-way VLIW Processor
作者: 張瑞宏
Chang, Jui-Hung
陳昌居
Chen, Chang-Jiu
資訊科學與工程研究所
關鍵字: 非同步處理器;指令壓縮;asynchronous processor;instruction compression
公開日期: 2010
摘要: 超大指令字組(VLIW)的概念是一次固定發出多道指令讓處理器同時執行,本論文採用雙道指令,並且以非同步電路方式針對指令壓縮做設計。目前嵌入式系統中常使用VLIW,這種方法主要是利用編譯器做運算單元的分配,以簡化電路。另外,以非同步電路方式設計的主要目的是降低功耗。其實,在VLIW架構下常因為指令無法平行執行,導致指令記憶體空間的浪費,因此將指令壓縮成為常見的作法。 非同步處理器與一般的處理器不同,它會佔用較大的電路面積,因此不適合複雜的壓縮機制。因此,本論文針對非同步電路特性,提出一個適合的指令壓縮設計。另外,為配合特殊的指令設計,本論文亦精簡部分所需電路。此外還針對處理器的一半管線利用率,設計出簡單且有效率的跳躍指令處理方式。最後我們的實驗結果顯示,依據程式平行度的不同,有60%左右的壓縮比,而處理解壓縮部份的面積僅佔整個處理器的2.8%。
The concept of VLIW is multiple instruction issue. The compiler is responsible for distribution of function unit. Thus VLIW suits embedded system because of the simple circuit. In this thesis, we design instruction compression for asynchronous two-way VLIW processor. We use asynchronous design style to lower power consumption. Unfortunately, there is a problem about VLIW architecture. It wastes instruction memory while the instruction packet cannot be parallelly executed. So it is common view to compress instruction packet. Asynchronous processor occupies bigger circuit area compared to general processor. It does not suit complex compression mechanism. We adopted suitable instruction compression way for asynchronous processor with novel implementation. We also design special instruction set to simplify the circuit. Moreover we design simple and efficient branch handling based on 50% pipeline utilization. In our implementation, we get approximately 60% compression ratio with 2.8% area overhead.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079755625
http://hdl.handle.net/11536/45970
Appears in Collections:Thesis


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