標題: 非同步雙道超大指令字組處理器之預解碼迴圈緩衝器設計
Predecode Loop Buffer Design for Asynchronous two-way VLIW Processor
作者: 陳建志
Chen, Jian-Jhih
陳昌居
Chen, Chang-Jiu
資訊科學與工程研究所
關鍵字: 非同步;超大指令字組;迴圈緩衝器;雙道;Asynchronous;VLIW;Loop Buffer;Dualrail
公開日期: 2010
摘要: 現今處理器採用的電路多為同步電路,也就是由時脈驅動的電路。時脈會造成時脈偏差的問題,非同步電路是一種沒有時脈的電路,所以非同步電路設計可以避免時脈產生的時脈偏差問題。迴圈緩衝器設計在現今的數位訊號處理器或者嵌入式處理器中,是一個非常普遍且實用的元件。迴圈緩衝器不僅能減少指令記憶體的存取次數,更能達到增進效能。 然而,傳統的迴圈緩衝器中的迴圈偵測機制,卻往往造成一個經常執行的指令被執行頻率不高的指令替換因此本篇論文設計了一個新穎的迴圈偵測機制,不僅能避免執行頻率高的迴圈被替換,更能減少指令解碼單元部分運算。 我們將預解碼迴圈緩衝器實現在一款無時脈的非同步雙道超大指令字組處理器。 我們使用Design Compiler合成,預解碼迴圈緩衝器合成所產生的結果為面積240000μm 、延遲7.41 ns。
Most modern processors are synchronous circuit that is triggered by clock. Clock would produce the problem that is clock skew. Asynchronous circuit is clockless and the problem of clock skew it can be avoided by handshake protocol. Loop buffer design is a common and useful unit for modern digital signal processors or embedded processors. It is not only could decrease the access times of instruction memory, but could improve performance. However, traditional loop buffers always let the frequently executed instruction be replaced by another infrequently executed instruction. Thus, this thesis designs a novel loop detection that could avoid a frequently executed instruction be replaced and reduce the operations of instruction fetch and decode. Predecode Loop Buffer will be implemented on asynchronous two-way VLIW processor. Predecode Loop Buffer is synthesized by Design Compiler. Its area is about 240000μm and its delay is 7.41 ns.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079755621
http://hdl.handle.net/11536/45966
Appears in Collections:Thesis


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