Characteristics of Poly-Si Nanowire TFTs With Asymmetric Ω-Gate
元件完成後，比較Ω式閘極結構和非對稱式閘極結構的元件特性，發現改變非對稱結構的比例時，能夠有效改善元件特性。當非對稱結構比例高時，元件特性趨近於三重閘極，比例低時元件則有Ω式閘極結構特性，包括高驅動電流，低次臨界擺幅，較高的開關比，低閘極引發汲極漏電流(Gate Induced Drain Leakage)和抑制短通道效應。這說明本實驗成功地融合三重閘極和Ω式閘極的元件特性，並有效抑制漏電流和關閉電流，良好地提升元件整體的電性。|
In order to increase the gate control capacity on the channel, multi-gate structure has been extensively studied as the critical dimension of thin-film transistors (TFTs) is scaled down. Both gate-all-around (GAA) TFTs and TFT SONOS memory devices have been demonstrated previously with excellent channel controllability and outstanding memory properties. On the base of previous research, polysilicon nanowire transistors with Ω-Gate have been proposed in this study. The Ω-Gate structure exhibits good controllability on channel presumably due to the coverage of four corners of device channel. Moreover, an asymmetric gate structure by converting one side of Ω-Gate into Tri-Gate such that lower leakage current and off state current enhanced. A comparison on the characteristics of both Ω-Gate devices and asymmetric Ω-Gate device were performed. It is found that changing the ratio of asymmetric structure can effectively change the device characteristics. When in high proportion of asymmetric structure, the device characteristics close to the Tri-Gate, and for low proportion of asymmetric structure, devices exhibit characteristics like Ω-Gate devices which possess properties including a high driving current, a steep subthreshold swing, a high on/off current ratio, low gate induced drain leakage (GIDL),and short channel effect suppression(SCE). The proposed asymmetric gate devices, combining Tri-gate and Ω-Gate, successfully inhibit the leakage current and suppress off-state current, and enhance the overall electrical properties.