標題: 非對稱Ω式閘極多晶矽奈米線薄膜電晶體之特性
Characteristics of Poly-Si Nanowire TFTs With Asymmetric Ω-Gate
作者: 羅以倫
Luo, E-Lun
許鉦宗
Sheu, Jeng-Tzong
材料科學與工程學系奈米科技碩博士班
關鍵字: 多晶矽;奈米線;Ω式閘極;非對稱;Poly-Si;Nanowire;Ω-Gate;Asymmetric
公開日期: 2010
摘要: 近年來電晶體的尺度日漸縮小,為了增加閘極對通道的掌控能力,從傳統的微米級通道轉變為奈米級通道,且多重閘極結構被廣泛的研究。本實驗室之前已經利用環繞式閘極成功地和記憶體結合,利用其優秀的通道掌控能力,抑制了通道微小化後的問題。本實驗建立於之前的研究上,將環繞式閘極結構的多晶矽奈米線電晶體應用到Ω式閘極多晶矽奈米線電晶體,除了有環繞式結構元件的特性,亦包覆著通道的四個角落,有良好的控制能力,之後並將三重閘極和Ω式閘極作結合,改良成非對稱式Ω式閘極多晶矽奈米線電晶體,除了維持原先良好的通道控制能力,並有較低的漏電流和關閉狀態,提升元件整體特性。 元件完成後,比較Ω式閘極結構和非對稱式閘極結構的元件特性,發現改變非對稱結構的比例時,能夠有效改善元件特性。當非對稱結構比例高時,元件特性趨近於三重閘極,比例低時元件則有Ω式閘極結構特性,包括高驅動電流,低次臨界擺幅,較高的開關比,低閘極引發汲極漏電流(Gate Induced Drain Leakage)和抑制短通道效應。這說明本實驗成功地融合三重閘極和Ω式閘極的元件特性,並有效抑制漏電流和關閉電流,良好地提升元件整體的電性。
In order to increase the gate control capacity on the channel, multi-gate structure has been extensively studied as the critical dimension of thin-film transistors (TFTs) is scaled down. Both gate-all-around (GAA) TFTs and TFT SONOS memory devices have been demonstrated previously with excellent channel controllability and outstanding memory properties. On the base of previous research, polysilicon nanowire transistors with Ω-Gate have been proposed in this study. The Ω-Gate structure exhibits good controllability on channel presumably due to the coverage of four corners of device channel. Moreover, an asymmetric gate structure by converting one side of Ω-Gate into Tri-Gate such that lower leakage current and off state current enhanced. A comparison on the characteristics of both Ω-Gate devices and asymmetric Ω-Gate device were performed. It is found that changing the ratio of asymmetric structure can effectively change the device characteristics. When in high proportion of asymmetric structure, the device characteristics close to the Tri-Gate, and for low proportion of asymmetric structure, devices exhibit characteristics like Ω-Gate devices which possess properties including a high driving current, a steep subthreshold swing, a high on/off current ratio, low gate induced drain leakage (GIDL),and short channel effect suppression(SCE). The proposed asymmetric gate devices, combining Tri-gate and Ω-Gate, successfully inhibit the leakage current and suppress off-state current, and enhance the overall electrical properties.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079752513
http://hdl.handle.net/11536/45838
顯示於類別:畢業論文


文件中的檔案:

  1. 251301.pdf
  2. 251302.pdf