標題: 16奈米場效應電晶體特性擾動抑制暨TFT-LCD驅動電路設計優化之研究
Suppression of 16-nm MOSFET Characteristic Fluctuation and Design Optimization of TFT-LCD ASG Driver Circuit
作者: 李國輔
Lee, Kuo-Fu
李義明
Li, Yiming
電信工程研究所
關鍵字: 隨機離散摻雜;複合式材料閘極元件;非對稱通道摻雜元件;基因演算法;非晶矽閘極驅動電路;上升時間;下降時間;漣漪電壓;random dopants;dual materials gate;lateral asymmetric channel device;genetic algorithm;a-Si gate driver circuit;rise time;fall time;ripple voltage
公開日期: 2010
摘要: 本論文主要分為兩部份,這兩部份皆與類比暨前瞻通訊應用上有相關性,其中甲部分為半導體16奈米場效應電晶體特性擾動抑制分析,乙部分為TFT-LCD驅動電路設計優化之研究。分述如下: 甲部分: 隨著手機應用越來越廣泛,使得頻率區段使用變的極為競爭且激烈,然而高頻段區域尚未有使用執照的限定與規範,因此為了提升動態特性,就加速了半導體元件微縮在類比電路上的應用。 但是伴隨著金屬氧化半導體場效應電晶體(MOSFET)元件通道尺寸依循摩爾定律被迅速缩小,元件特性變異成為主要挑戰且對電路設計上極為重要。而隨機離散摻雜所導致的擾動(RDF)是這些特性變異的主要來源。透過檢驗元件變異所造成類比電路上的特性變異便成極迫切的議題,在16奈米技術上去壓抑隨機離散摻雜所造成的特性擾動是個熱門的研究方向。 在本研究中,我們首次探討了兩種不同的雙邊非對稱金屬閘極元件來壓抑由16奈米金屬氧化半導體場效應電晶體 (MOSFET)元件隨機摻雜效應(RDF)所導致在元件直流(DC)特性擾動,例如:臨界電壓(Vth)、導通電流(Ion)、夾止電流(Ioff)等等。然而同樣的壓抑現象卻不能實現在非對稱雙金屬閘極(DMG)元件的交流(AC)特性上,例如電容(Cg)。這是因為空乏區电容是被通道區域的摻雜分佈和有效的氧化層厚度所影響。為了有效壓抑離散隨機摻雜所導致的交流特性擾動,我們進一步探討16奈米隨機摻雜分佈的元件的非對稱現象,主要分為靠近源極端摻雜和汲極端的摻雜。在通道區域中靠近源極端離散摻雜和靠近汲極端離散摻雜導致不同閘極電容和動態特性的擾動。基於所觀察到的非對稱特性,我們使用此横向不對稱性通道摻雜分佈的方法來壓抑在元件和電路由隨機摻雜所導致的擾動。本研究結果發現,在靠近汲極端離散摻雜的元件和一般所使用的元件比較中,臨界電壓擾動(□Vth)、導通電流擾動(□Ion)、電導擾動 (□gm)、元件阻抗擾動(□ro)、閘極電容擾動 (□Cg)、電路增益擾動、3dB 頻寬擾動以及单位增益擾動,同時分別降低33.4%, 32.8%, 11.9%, 80.6%, 68.8%, 31.2%, 37.6% 和 47%。所以這樣的横向不對稱通道摻雜可以有效使用來設計壓抑電晶體的特性擾動。 乙部分: 近年來,隨著面板產業的蓬勃發展,非晶矽薄膜電晶體液晶顯示器(a-Si:H TFT-LCD)已被廣泛應用於手機之顯示系統。而以非晶矽薄膜電晶體為元件的閘極驅動電路(TFT-ASG circuit),在薄膜電晶體液體顯示器(TFT-LCD)面板的製造上已扮演重要的角色。但是,設計薄膜液晶顯示器面板驅動電路的工作是相當複雜以及費時,工程師必須不斷地調整電晶體參數以滿足節能產品之需求,像是:降低充放電的時間、降低漣漪電壓以及降低消耗等顯示規格。 在這篇論文中,我們使用兩個不同的電路架構來改善動態特性並且對這些動態特性進行電晶體尺寸的最佳化。所使用的最佳化技巧主要是在統合性的最佳化架構下,以模擬為基礎並結合基因演算法與電路模擬器的演化式方法。其中第一個含有14顆TFT的電路除了設計上要求上升時間及下降時間小於1.5微秒,漣漪電壓小於3伏特之外,也同時考慮電路面積的最小化;此電路主要用於大型面顯示器。第二個含有8顆TFT及2顆電容的電路不僅設計上要求上升時間、下降時間以及漣漪電壓小於2微秒和2伏特外,還多增加了功率小於2毫瓦特的要求;此電路主要用於手機面板。經過最佳化的結果,所有動態特性和功率消耗全部符合預期所設定的限制。並且在含有14顆TFT電路的總元件尺寸上有35%的降低,而經過敏感度分析測試之後,更發現這些最佳參數具有優異的穩定性。 接著使用標準的TFT 4微米的製程技術,將這些最佳化過後的電路一一實做出來進行動態特性量測與分析,14顆TFT電路在量測分析中上升和下降時間均維持在要求的規格中,並且在漣漪電壓上有71%的改善,模擬與實際量測誤差值更是相符合,而在8顆TFT電路上,上升和下降時間也均符合規格要求,漣漪電壓更是有49%上之改善,另外值得注意的是與原始對照組的電路面積比較,最佳過後的電路面積更是微縮了36%之多。 透過統合性的最佳化架構,以模擬為基礎並結合基因演算法與電路模擬器的演化式方法,自動調整電晶體參數來最佳化面板閘極驅動電路的設計,這將對面板市場和閘極電路設計獲益良多。 總而言之,不管是甲部分還是乙部分,本論文的研究對目前台灣兩兆雙星產業:半導體和面板帶來技術諸多優勢以及經濟利潤許多遠景。
This thesis consists of two research topics: the suppression of 16-nmMOSFET characteristic fluctuation and design optimization of TFT-LCD amorphous silicon gate (ASG) driver circuit. The abstract of each study is organized as follows. PART A : As theminimumfeature size of metal-oxide-semiconductor field effect transistor (MOSFET) has been rapidly scaled down, characteristic variability becomes a major challenge to device technologies and crucial for circuit design. The random dopant fluctuation (RDF) has shown as the major source of variation. It is stringent to examine the device-variability induced characteristic fluctuations of analog circuit and suppression of RD-induced threshold voltage (Vth) fluctuation is urgent for 16-nm device technologies. In this part, we for the first time explore the dual materials gate (DMG) and inverse DMG (inDMG) devices for suppressing RDF-induced DC characteristics fluctuation in 16-nm MOSFET devices. However, the same phenomenon can not enjoy the advantage in AC characteristics of DMG device because the capacitance of depletion region is affected by doping distribution of channel region and effective oxide thickness. Then, we further explore the asymmetric sketch of random dopants distribution near the source end and the drain end in 16 nm MOSFETs. Discrete dopants near the source and drain ends of channel region induce rather different fluctuations in gate capacitance and dynamic characteristics. Based upon the observed asymmetry properties, a lateral asymmetry channel doping profile engineering is then proposed to suppress the random-dopant-induced characteristic fluctuations in the examined devices and circuits. The results of this study indicate the fluctuations of threshold voltage (Vth), on-current (Ion), transconductance (gm), intrinsic output resistance (ro), gate capacitance (Cg), circuit gain, 3dB bandwidth, and unity-gain bandwidth for the cases with dopants near the drain side could be simultaneously reduced by 33.4%, 32.8%, 11.9%, 80.6%, 68.8%, 31.2%, 37.6% and 47%, respectively. Consequently, such lateral asymmetry channel doping profile could be considered to design intrinsic parameter fluctuation resistant transistors. PART B : Recently, a-Si:H thin film transistor liquid-crystal display (a-Si:H TFT-LCD) has been widely used in display system of mobile phone. For TFT-LCD panel manufacturing, gate driver circuit with hydrogenated amorphous silicon thin-film transistor (TFT-ASG circuit) plays an important role. Unfortunately, to meet specified display performances of product, such as low power display system, high dynamic characteristics, and so on, system designers have to manually and iteratively adjust the designing parameters of the a-Si:H TFT-ASG driver circuit, which make the design of a-Si:H TFT-ASG driver circuit system complicated and time-consuming. In this part, we propose two different ASG driver circuit topologies to improve circuits’ dynamic characteristics. The optimization work is conducted by the adopted simulation-based evolutionary method integrating genetic algorithm and circuit simulator on the unified optimization framework. The first circuit consisting of fourteen hydrogenated amorphous silicon TFTs (a-Si:H TFTs) used in a large panel is optimized for the specifications of the rise time < 1.5 μs, the fall time < 1.5 μs and the ripple voltage < 3 V with the minimization of total layout area. The second one with eight a-Si:H TFTs and two capacitors used in a display panel of mobile phone is optimized with the further condition that power dissipation < 2 mW. By optimizing the devices’ width and passive components, the optimized results of this study successfully meet the desired specifications, where the sensitivity analysis is conducted to verify the characteristic variation with respect to the optimized parameters. To validate the results, the optimized circuits are fabricated in standard 4-μm a-Si:H TFT technology and the experimental results confirm the practicability of achieved design. The ripple voltage of 1.9 V is successfully obtained while the rise and fall times satisfying the required specifications for the first circuit’s fabricated sample. A 35% reduction of the optimized total devices width of a-Si:H TFTs is also achieved. For the second circuit, the 49% improvement of ripple voltage and 36% reduction of circuit area are obtained from fabricated sample. In summary, we have studied two important issues for advance semiconductor and current photonics industries. The results of these studies may benefit 16-nm MOSFET technologies and TFT-LCD circuit design.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079713618
http://hdl.handle.net/11536/44636
顯示於類別:畢業論文


文件中的檔案:

  1. 361801.pdf