標題: 使用摺疊電壓隨耦器以提升線性度之互補金氧半轉導放大器設計
CMOS Operational Transconductance Amplifiers with Linearity Improving by Flipped Voltage Follower
作者: 陳伽維
Chen, Chia-Wei
洪崇智
Hung, Chung-Chih
電信工程研究所
關鍵字: 轉導放大器;Transconductor
公開日期: 2010
摘要: 近年來因為CMOS製程的發展,跟隨而來的短通道效應已經改變了許多類比電路的設計,因為製程由深次微米朝向奈米技術發展,短通道效應變成了一個主要的設計課題。短通道效應影響轉導放大器的線性度效能越來越明顯,而電晶體飽和區的公式將會受到短通道效應的嚴重影響,因此許多由理想電流公式所衍伸出的傳統轉導放大器架構在先進的製程中所受到的非理想效應,比起過去製程將會更多。 本論文提出兩種以減少非理想的小信號電阻之方法提升線性度,用以補償短通道效應所產生之非線性諧波成分。此外,本論文將介紹轉導放大器的主要應用:轉導電容式濾波器。於論文最後,將介紹一個轉導電容式四階低通濾波器的設計過程與完成。 本文提出的第一個轉導放大器是基於源極退化架構的轉導放大器並以摺疊式翻轉電壓隨耦器及正回授的迴路增強其線性度。此轉導放大器以台積電0.18μm CMOS製程實現,其消耗功率3.7mW,工作電壓為1.8V。結果顯示當輸入信號為振幅為0.6Vpp且頻率10MHz時,達到第三次諧波失真為-70dB。此轉導放大器含接腳使用面積為0.5mm × 0.395mm。 本文提出的第二個轉導放大器是基於虛差動對輸入轉導放大器並以改進過的摺疊式翻轉電壓隨耦器增強其線性度。此轉導放大器以台積電0.18μm CMOS製程實現,其消耗功率0.7mW,工作電壓為1.8V。結果顯示當輸入信號為振幅為0.6Vpp且頻率10MHz時,達到第三次諧波失真為-78dB。此轉導放大器使用面積小於0.01 mm2。 使用此轉導放大器作為建構濾波器的區塊,製作一個頻率5Mhz的轉導電容式濾波器,此濾波器的諧波失真為-48dB,其消耗功率9.14mW,含接腳使用面積為0.502mm × 0.612mm。
In recent years, the short channel effect has changed the way of designing analog circuits, which becomes a main issue as the technology marches to deep-submicron fields. The impact of the short channel effect on the design of the operational transconductance amplifier (OTA) becomes more serious and makes the circuit performance deviated from the ideal voltage-current equation, especially the performance of the linearity. This paper presents two fully balanced structures of CMOS Operational Transconductance Amplifier (OTA) with high linearity, and its applications to Gm-C filters. The transconductors are designed for highly linear applications using methods which reduce non-ideal small signal resistance. The proposed first circuit based on the source-degeneration structure and enhanced with modified Folded Flipped Voltage Follower and positive feedback for linearity improving was designed by the TSMC 0.18μm CMOS technology and dissipates 3.7mW power with 1.8V voltage supply. The result shows the HD3 of -70dB with 0.6Vpp 10MHz input signal. It occupies the area of 0.5mm * 0.395mm, including pads. The proposed second circuit based on the conventional pseudo-differential structure and enhanced with modified Folded Flipped Voltage Follower for linearity improving was designed by the TSMC 0.18μm CMOS technology and dissipates 0.7mW power with 1.8V voltage supply. The result shows the HD3 of -58dB with 0.6Vpp 10MHz input signal. The active area uses less than 0.01 mm2. Using this OTA as building blocks, a 5MHz Gm-C low-pass filter was designed with the HD3 of -48dB. It consumes 9.14mW and occupies the area of 0.502mm * 0.612mm, including pads.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079713613
http://hdl.handle.net/11536/44630
顯示於類別:畢業論文


文件中的檔案:

  1. 361301.pdf