標題: 應用於硬碟讀取通道技術及液晶顯示器源極驅動器之資料轉換器
Data Converters for PRML Read Channel and LCD Column Driver Applications
作者: 李人維
Li, Ren-Wei
洪崇智
Hung, Chung-Chih
電信工程研究所
關鍵字: 類比數位轉換器;快閃式轉換器;偏移誤差平均技巧;數位類比轉換器;電荷重新分佈數位類比轉換器;序向式數位類比轉換器;ADC;A/D converter;flash converter;offset averaging;D/A converter;Charge redistribution DAC;cyclic DAC;DAC
公開日期: 2010
摘要: 系統中,類比數位轉換器的效能與功率消耗對整體系統的效率具有重要的影響。本篇論文著重於極高速類比數位轉換器的設計考量,並提出一個六位元之快閃式類比數位轉換器的設計,其使用電阻式平均網路技巧去除輸入偏差。此電路包含了一個追蹤保持電路來消除因為時脈訊號及輸入訊號傳遞到眾多比較器所造成的取樣時間誤差,以提高其動態效能。另外,針對數位編碼器在高速下的穩定操作,我們也做了精密的考量。 傳統上,液晶顯示器的源極驅動器都是採用非線性電阻串式數位類比轉換器。本篇論文是採用切換電容式數位類比轉換器,其每一位元的轉換時間為五微秒,以及僅僅消耗不到兩微安培的電流量。在面積方面,與傳統電阻式數位類比轉換器比較之下,更是有著大幅度的縮減,也不會因解析度的提高而使面積成指數型式成長。
Performance and power consumption of analog-to-digital converters (ADCs) affect the efficiency of an entire system. In this thesis, we focus on the development of the design techniques for high speed ADCs, and propose a 6-bit high speed ADC design using resistive averaging techniques. The ADC includes an on-chip Track/Hold circuit to eliminate the sampling time skews resulted from the fact that the clock and input signal are transmitted to numerous comparators, and further enhance the dynamic performance. In addition, there are elaborated considerations made for enabling digital encoders to be operated stably at high speed. LCD column drivers have traditionally used the nonlinear R-string style digital-to-analog converter (DAC). This thesis describes a switch capacitor digital-to-analog converter, which transfers one bit within 5us and consumes less than 2uA. Compared with the traditional digital-to-analog converter, there is a substantial reduction on areas. And when the resolution increases, the area does not grow exponentially.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079713612
http://hdl.handle.net/11536/44629
顯示於類別:畢業論文


文件中的檔案:

  1. 361201.pdf