標題: 應用於超寬頻通訊系統之互補式金氧半毫米波積體電路設計與分析
The Design and Analysis of CMOS Millimeter-Wave Integrated Circuits for Ultra-Wideband Communication Systems
作者: 虞繼堯
吳重雨
電子研究所
關鍵字: 毫米波;互補式金氧半積體電路;超寬頻系統;Millimeter Wave;CMOS Integrated Circuit;UWB system
公開日期: 2007
摘要: 可預期的,未來利用無線傳輸的資料量與其所需頻寬將與日俱增,因此毫米波頻段的超寬頻系統在個人通訊上的使用亦將無可避免。針對此應用,本論文提出了數種互補式金氧半製程關鍵積體電路元件的架構、設計方式與分析,其中包含了 (1) 直接注入式鎖定除頻器的模組、分析與設計,(2) 應用於降頻的三階諧波主動式混波器,(3) 直接降頻接收機前置電路的設計與分析,(4)一個適用於毫米波頻段的多頻段寬頻壓控震盪器。而另一個射頻頻段的低電壓多頻段寬頻壓控震盪器也在此提出。 首先,本論文將分析適用於毫米波頻段的直接注入式鎖定除頻器,並且將建立其等效模組,利用此模組將可歸納出數個設計規則用以最佳化除頻器的效能,如頻率鎖定範圍。為了驗證所提出的等效模組與設計規則,一個不使用可變電容的直接注入式鎖定除頻器採用了0.13微米的互補式金氧半製程來製作。在此除頻器中,P型電晶體電流源將用以限制其輸出電壓振幅與增加輸入電晶體的直流驅動跨壓以加大頻率鎖定範圍。此除頻器的輸入電晶體長寬分別僅為0.12與3.6微米,而所量測到的中心頻率與頻率鎖定範圍分別為70GHz與13.6%。在1V的工作電壓下,其功率消耗為4.4mW。 其次,本論文提出了一個應用於降頻的三階諧波主動式混波器與其設計考量。此混波器所需的本地振盪頻率僅為傳統基頻混波器的三分之一。因此,與此混波器整合的壓控震盪器之頻率操作範圍將可被大幅的增進。再者,由於所提出之混波器利用本地振盪訊號的三階諧波降頻,而三階諧波的極性特徵與基頻完全相同,因此此混波器將可基頻混波器一樣輕易的擁有平衡架構。此混波器與一整合的壓控震盪器採用了0.13微米的互補式金氧半製程製作。量測結果顯示整合壓控震盪器的中心頻率為19.48GHz而頻率操作範圍可達13.35%,其相對應的射頻頻率可由54.54GHz至62.34GHz。在此射頻頻率範圍中,混波器的平均增益為7.8dB,且增益變化不超過2.2dB。其1dB增益下降點約為-10.2dBm,而在1.2V的工作電壓下,其與壓控震盪器平均功率消耗分別為6.6與0.36mW。 再其次,利用所提出之三階諧波主動式混波器,本論文提出了一個適用於毫米波頻段超寬頻系統的直接降頻接收機,並且使用0.13微米互補式金氧半製程設計。此接收機包含了一個低雜訊放大器、一對三階諧波主動式混波器、基頻放大器、輸出級與一個正交壓控震盪器。由於使用三階諧波混波器而降低了所需的本地震盪頻率,正交壓控震盪器的頻率操作範圍將可被大幅的增進。模擬結果顯示,當中心頻率為20.35GHz時,正交壓控震盪器的頻率操作範圍可達19.87%,其相對應的射頻頻率已足以涵蓋整個毫米波於美國之開放頻段,57 – 64GHz。 而在此頻段中,接收機的增益在25至29.25dB間,且其雜訊指數在 11.1至13.4dB間。接收機的1dB增益下降點約為-28dBm,而正交壓控震盪器在操作頻段中1MHz偏移頻率的平均相位雜訊為-96dBc/Hz。接收機的工作電壓為1.2V,平均功率消耗為35.6mW。 最後,本論文提出了兩個不同的多頻段寬頻壓控震盪器。其中之一適用於毫米波頻段。其使用可變電感調整振盪頻率。使用此可變電感調整振盪頻率,壓控振盪器將可擁有寬頻且多頻段的特性,且其振盪頻率亦不會因此而有所犧牲。利用90奈米互補式金氧半製程設計與製作,量測結果顯示,所提出之壓控振盪器的振盪頻率可由52.2調整至61.3GHz。相對應的中心頻率與調整範圍則分別為為56.75GHz與16%。當振盪頻率為61.3GHz時,10MHz偏移頻率的相位雜訊為-118dBc/Hz,而振幅約為-4.55dBV。在0.7V的工作電壓下,其功率消耗為8.7mW,晶片面積為0.28×0.36平方公釐。 另一個所提出的多頻段寬頻壓控震盪器則適用於數GHz的射頻頻段與低電壓操作。除了射頻頻段的應用外,此壓控震盪器亦可做為毫米波外差式接收機的中頻本地振盪訊號源。其使用了反轉型電晶體可變電容且利用一個大電阻隔絕基底的寄身效應以增大頻率調整範圍。為了降低壓控震盪器增益以增進相位雜訊效能,此壓控震盪器亦使用了多頻帶切換技術。以0.18微米互補式金氧半製程設計,模擬結果顯示,當工作電壓與頻率調整電壓均為0.8V時,其頻率調整範圍可由4.4至5.9GHz,調整百分比為29.12%。當振盪頻率為5.52GHz時,在1-MHz偏移頻率的相位雜訊為-109.65dBc/Hz,功率消耗為1.2mW。 經由模擬與量測結果證實,本論文所提出的關鍵積體電路元件將可用於高效能、高整合度、全補式金氧半製程的毫米波頻段超寬頻無線通訊系統中。在未來將針對其他的毫米波頻段積體電路元件整合而成為一個完整的收發器。
In this thesis, the design methodologies and implementation techniques of CMOS integrated circuits (ICs) for millimeter-wave (MMW) ultra-wideband (UWB) applications are presented. There are four different kinds of MMW ICs presented in this thesis, including: 1) a direct injection-locked frequency divider; 2) a down-conversion third-order sub-harmonic active mixer; 3) a MMW UWB homodyne receiver front-end; and 4) two multi-band voltage-controlled oscillators (VCOs) with a large frequency tuning range in MMW band and RF band for low-voltage applications. At first, direct injection-locked frequency dividers operated in the millimeter-wave band are analyzed. An analytically equivalent model of the direct injection-locked frequency dividers is developed and important design guidelines for a large frequency locking range are obtained. A direct injection-locked frequency divider without varactors is designed and fabricated using 0.13-μm bulk- CMOS process to verify the developed model and design guidelines. The size of the input device is only 3.6μm/0.12μm and the measured frequency locking range is 13.6% at 70GHz with a power consumption of 4.4mW from a supply voltage of 1V. Secondly, a down-conversion third-order sub-harmonic active mixer is analyzed and fabricated with an on-chip VCO using 0.13-μm CMOS technology. The required LO frequency is one third of that required in a fundamental mixer. Because of the decrease in the LO frequency, the frequency tuning range of the integrated VCO can be extended significantly. Moreover, with the essential differential characteristics of the third harmonic components of LO signals, a balanced structure can be achieved without any extra effort as a fundamental mixer. From the measurement results, it can be observed that the tuning range of the VCO is 13.35% at 19.48 GHz with the corresponding RF frequency range from 54.54 to 62.34 GHz. The average gain of the proposed mixer is 7.8 dB and the variation is smaller than 2.2 dB within the tuning range. The input 1-dB compression point is around –10.2 dBm and the power leakage of the 2LO/LO signal at the RF port is smaller than –35/–42.5 dBm, respectively. The average power consumption of the VCO and the mixer core within the operating frequency range are 6.6 and 0.36 mW, respectively. Thirdly, a homodyne receiver using third-order sub-harmonic active mixers is analyzed and designed by using 0.13-μm CMOS technology. The receiver consists of a low-noise amplifier (LNA), sub-harmonic active mixers, baseband amplifiers, output buffers, and a qudrature VCO. Due to the reduction in the required LO frequency by using the sub-harmonic mixers, the frequency tuning range of the integrated quadrature VCO can be significantly extended. From ADS and SpectreRF simulation results, the frequency tuning range of the qudrature VCO is 19.87% at 20.35 GHz and the corresponding RF frequency range is sufficient to cover the entire MMW unlicensed band in the U.S. (i.e. 57 – 64 GHz). The gain of the receiver within the unlicensed band is form 25 to 29.25 dB and the noise figure is from 11.1 to 13.4 dB. The 1-dB compression point occurs around -28 dBm. The phase noise of the quadrature VCO at 1-MHz offset is -96 dBc/Hz. The average power consumption of the receiver is 35.6 mW from a supply voltage of 1.2 V. Finally, two different multi-band VCOs with wide tuning range are proposed. One of them is operated in the MMW band. It employs a single variable inductor for frequency tuning. By employing the proposed frequency tuning scheme, wide-tuning range as well as multi-band operations are achieved without sacrificing its operating frequency. Fabricated in a 90-nm CMOS process, the VCO is capable of covering frequency range from 52.2 to 61.3 GHz. The tuning percentage is 16% at 56.75 GHz. The measured average phase noise within the tuning range is about -102.4 dBc/Hz at 10-MHz offset. The maximum oscillation voltage amplitude is around -4.55 dBV. The VCO core dissipates 8.7 mW from a 0.7-V supply. Chip size is 0.28 × 0.36 mm2. The other VCO is operated around 5 GHz which can be chosen as the intermediate frequency in an MMW heterodyne receiver. In this situation, the designed VCO can be used as the LO signal generator in the MMW heterodyne receiver to downconvert the intermediate frequency signals to the baseband. Inversion-mode MOS (I-MOS) varactors are used in the VCO to maintain a wide tuning range in the situation that the supply and tuning voltage is lower than 1V. Moreover, a large resistor is inserted between ground and bulk terminals of each I-MOS varactor to further improve the tuning capability. Through this resistor, the tuning range is increased by 500 MHz (50%). A bandswitching topology is used to ameliorate the adverse effects of highly sensitive I-MOS varactors. The VCO is designed using 0.18-μm CMOS technology. With a 0.8-V supply, it is shown from simulation results that the VCO has a tuning range of 29.12% from 4.4 to 5.9 GHz when tuned from 0 to 0.8 V. The simulated phase noise is -109.65 dBc/Hz at 1-MHz offset from the 5.52-GHz carrier. The power consumption is 1.2 mW. It is believed that the proposed IC components can be applied to the design of high-performance high-integration all-CMOS wireless communication systems for MMW UWB applications. Further research on the integration of other transceiver components to form all-CMOS MMW UWB systems will be conducted in the future.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009111846
http://hdl.handle.net/11536/44490
Appears in Collections:Thesis


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