Low Power and High Speed SRAM with Current-Mode Techniques
|關鍵字:||電流模式;感測放大器;寫入驅動器;靜態隨機存取記憶體;current-mode;sense amplifier;write driver;SRAM|
This thesis explores the design and analysis of Static Random Access Memories (SRAMs) and focuses on low power operation. The SRAM access path is split into three portions: from address input to word line rise (the write operation), from word line rise to data output (the read path) and memory cell. The techniques to optimize both of these paths are investigated. The voltage-controlled negative-differential-resistance device by using a merged integrated circuit of n-channel MOSFET and parasitic NPN bipolar transistor, called Lambda bipolar transistor (LBT), is known for its memory application. In this thesis, a new LBT structure is developed and its characteristics are derived by simple circuit model and device physics. A novel single-sided memory cell based on the proposed LBT’s is presented. High performance and low power SRAM design always focuses on reducing dynamic power dissipation at the operating state and decreasing DC current and leakage current at the standby state. To reduce operation power without decreasing read/write speed, we propose special current-mode read/write mechanism instead of conventional voltage-mode circuits. In this thesis, a new current-mode sense amplifier is proposed to sense the bit-line signal even though the voltage swing of the bit-line is small, and the non-floating design reduces noise produced during sensing in the standby mode. The current-mode write driver can reduce the bit-line swing when data write in, not only decreasing power consumption but also speeding up writing access time. Using new current-mode techniques for read and write operation, the sensing speed and write pulse width are insensitive to the bit-line and data-line capacitances and a separated positive feedback technique is used to enable the circuit to operate at high-speed and low-power. These techniques always keep the voltage swing of the bit-line and data-line quite small. Based on current-mode operation, a memory cell that operates at low-power current-mode is developed. The memory cell has almost equally sized access and inverter transistors, which can be toggled using a small differential bit-line voltage. The presented techniques were demonstrated to be useful by evaluating an experimental 32Kx8 SRAM chip using 0.35um 1P2M CMOS process technology. An experimental 32Kx8 CMOS SRAM with a 9ns access time at a supply voltage of 3V is described to evaluate the new current-mode techniques. The active current is 28mA at 100MHz and 25℃.
|Appears in Collections:||Thesis|
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