標題: 應用於H.264/AVC視訊解碼器之低功耗反整數轉換
Design of A Low Power Inverse Integer Transform for H.264/AVC Decoding Applications
作者: 王英杰
Huseyin Demirkaya
李鎮宜
Lee, C.Y.
電子研究所
關鍵字: 應用於H.264/AVC視訊解碼器之低功耗反整數轉換;inverse integer transform,H.264
公開日期: 2010
摘要: In this thesis, we adopted various new fast butterfly algorithms and hardware architectures for low power Inverse Integer Transform (IIT) in H.264/AVC Main/High Profile video decoding. In our new fast algorithms we use matrix decomposition method to reduce the complexity of inverse integer transforms to reduce the power consumption, hardware cost and raise hardware efficiency in H.264/AVC Main/High Profile video decoding. Matrix decomposition utilizes the permutation matrices. The proposed design supports 4x4, 2x2/4x4 Hadamard and 8x8 inverse transforms. We integrate the same parts of the three transforms to reduce the power consumption and hardware area and the cost. Finally, we can use the proposed hardware design to handle the video coding with the 1080 HD @30fps and also QFHD @30fps video format, and our hardware architectures which is used the new fast butterfly algorithms, power consumption for 4x4, Hadamard, and 8x8 inverse integer transform are 56.45μW, 46.85μW, 0.21mW, respectively. Thus, our design’s power consumption and hardware cost are smaller when comparing to previous works and also our designs just needs only 5.1% work time for the transforms. Then we have 94.9% rest time to support the other functions of the H.264/AVC. Thus, the proposed architecture has the capability to achieve the real-time processing of 1080 HD and QFHD @ 30fps video coding.
In this thesis, we adopted various new fast butterfly algorithms and hardware architectures for low power Inverse Integer Transform (IIT) in H.264/AVC Main/High Profile video decoding. In our new fast algorithms we use matrix decomposition method to reduce the complexity of inverse integer transforms to reduce the power consumption, hardware cost and raise hardware efficiency in H.264/AVC Main/High Profile video decoding. Matrix decomposition utilizes the permutation matrices. The proposed design supports 4x4, 2x2/4x4 Hadamard and 8x8 inverse transforms. We integrate the same parts of the three transforms to reduce the power consumption and hardware area and the cost. Finally, we can use the proposed hardware design to handle the video coding with the 1080 HD @30fps and also QFHD @30fps video format, and our hardware architectures which is used the new fast butterfly algorithms, power consumption for 4x4, Hadamard, and 8x8 inverse integer transform are 56.45μW, 46.85μW, 0.21mW, respectively. Thus, our design’s power consumption and hardware cost are smaller when comparing to previous works and also our designs just needs only 5.1% work time for the transforms. Then we have 94.9% rest time to support the other functions of the H.264/AVC. Thus, the proposed architecture has the capability to achieve the real-time processing of 1080 HD and QFHD @ 30fps video coding.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079711684
http://hdl.handle.net/11536/44380
Appears in Collections:Thesis


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