Title: 主動延遲電路的應用
The Applications of Active Delay circuits
Authors: 張佑偉
Keywords: 全通濾波器;主動延遲電路;延遲頻寬乘積;All-pass filter;Active delay circuit;Delay bandwidth product
Issue Date: 2010
Abstract: 在通訊系統的架構中,延遲功能為應用上重要的一部分。本論文針對2個不同的應用設計了3個主動延遲電路。 第一個部份為2個應用在WiMAX極座標發射器上具有可調時間延遲的訊號同步電路,電路分別以1階與2階有理式的數學模型來實現,為了後續整合而使用TSMC 0.35-um SiGe製程來設計。一階延遲電路的量測結果並沒有合乎預期。而在2階延遲電路的實現中,其特色是相較於1階電路有2倍的延遲頻寬。量測結果顯示,當操作電壓為3.3 V,核心電路的直流功率消耗為 21.8 mW,其電壓增益為 -1 dB以及有著1.09 ns的可調延遲時間。 第二個部分為應用在10 Gb/s等化器的寬頻延遲電路,使用TSMC 0.18-um CMOS製程來實現。模擬結果顯示核心電路在6.6 mW的消耗下,有 -1 dB的電壓增益及35 ps的時間延遲。另外,此電路有著寬頻的延遲響應使其在通訊系統整合上具有相當的潛力。
Delay function is an important part in the application of communication systems. In this thesis, three active delay circuits are designed based on two specific applications. The first part contains two tunable delay compensation circuits in polar loop transmitter for WiMAX applications. The circuits realize 1st-order and 2nd-order rational functions, respectively. To integrate with PA circuitry, both delay circuits are fabricated in TSMC 0.35-□m SiGe technology. Measurement results of 1st-order delay circuit are not as expected. In the application of the 2nd-order delay circuit, it features double delay bandwidth of the 1st-order delay circuit. The power consumption of its core circuit is 21.8 mW with 3.3 V supply. Measurement results show that the voltage gain is -1 dB, and the time difference between the consecutive steps is about 1.09 ns. In the second part, a wideband delay circuit for 10 Gb/s equalizer applications is implemented using TSMC 0.18-□m CMOS technology. Simulation results show -1 dB voltage gain and 35 ps delay under 6.6 mW power dissipation. In addition, this circuit with wide delay bandwidth has great potential in the integration of communication systems.
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