標題: 考量可偵錯式設計之版圖修正以利於進行聚焦離子束的訊號觀測與電路修正技術
Design-for-Debug Aware Layout Modification for FIB Net Observation and Circuit Editing
作者: 張琮偉
Chang, Tsung-Wei
周景揚
Jou, Jin-Yang
電子研究所
關鍵字: 可偵錯式設計;design-for-debug
公開日期: 2010
摘要: 在現今矽除錯之流程中,晶片的錯誤分析是相當重要的一個環節。錯誤分析結果的優劣,取決於當晶片運行時,所能得到的訊號數量:若所得到的數量越多,則找出錯誤發生位置的成功率越高。在現行錯誤分析的技術中,聚焦離子束的技術被廣泛使用,因其(1)可直接觀察訊號值、以及(2)可直接對晶片進行修改的特性,使得錯誤分析的效率得到大幅度的改善。然而,隨著製程的演進,金屬線的間距與寬度皆變小、金屬層的密度提高,導致我們難以對任意的訊號進行觀察或修改的操作,進而使得錯誤分析的難度提昇。為了解決這個問題,在此篇論文中,我們藉由預先修改繞線,以提高(1)觀察率以及(2)修改率。實驗數據的結果顯示,經由我們的方法修改過的設計,可提高平均約50%的觀察率,修改率亦是原先的兩倍以上。
Failure analysis}(FA) plays a critical role in today's silicon debugging flow. The efficiency of FA depends on how many net values can be observed while a chip is running. If we acquire more net values, locating the failure will become easier. On the contrary, few values of nets would result in more difficult FA. In modern techniques of FA, focus ion beam is widely used since it can directly observe net values and modify chips. These characteristics enhance the efficiency of FA. However, due to the advanced technologies, both the interval between each wire and width of wires become smaller. This phenomenon causes that observing and modifying arbitrary nets become more difficult. Thus, difficulty of FA will raise as well. To conquer this problem, we propose a methodology to modify the routing of a design in advance. In this manner, we can reach the goals: enhancing the (1)observing rate and (2)modifying rate. Our experimental results show that the improvement of observing rate reaches 50% on average and modifying rate doubled compared with the original design.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079711661
http://hdl.handle.net/11536/44362
Appears in Collections:Thesis


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  1. 166101.pdf