標題: 用於矽穿孔之三維積體電路完整電源供應之分析
Power Integrity in TSV 3D Integration
作者: 林天鴻
Lin, Tien-Hung
黃威
Hwang, Wei
電子研究所
關鍵字: 電源供應;雜訊抑制;三維積體電路;矽穿孔;Power integrity;TSV 3D
公開日期: 2009
摘要: 三維積體電路不但非常適合異質整合,更能夠提升系統整體的速度以及降低功率消耗。然而當大量的電流同時流過封裝及矽穿孔(TSV)所造成的雜訊是非常可怕的,因此如何設計一個穩定的電源供應系統是非常重要的。在本篇論文中,我們提出了一個有效率的設計電源矽穿孔(power TSV bundle)的方法。並且根據矽穿孔之三維積體電路的特性提出了一個使用主動藕荷電容的電源雜訊抑制的電路機制。最後提出一個低靜態電流的低壓降線性穩壓器(LDO)提供可調的低雜訊電源供應電壓,並使用基底雜訊抑制的機制來減少藉由基底所傳出的雜訊。利用UMC 65nm CMOS 以及TSV模型技術來實現電路設計與佈局。
Three-dimensional (3D) nanosystems can provide enormous advantages in achieving multi-functional integration, improving system speed and reducing power consumption for future generations of ICs. The robust power delivery system is very important in 3D ICs. In 3D integration, the increasing supply current through both package and through-silicon-via (TSV) would lead to a large simultaneous switching noise potentially. We will introduce basic 3D technology and a proposed design method for placing the TSV bundle in 3D IC under the efficiency condition. Next, the active supply noise regulation scheme is introduced; we propose the power noise suppression technique using active decoupling capacitor (DECAPs) for TSV 3D integration characteristic. Finally, a low quiescent current linear drop regulator (LDO) is proposed to provide difference supply voltage with low noise, and substrate noise canceller is used to suppress the impact of substrate noise. All simulations are based on UMC 65nm CMOS technology and TSV model at 1V supply voltage.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079711650
http://hdl.handle.net/11536/44351
Appears in Collections:Thesis


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