標題: 應用於超寬頻系統之低雜訊放大器之設計
Design Low Noise Amplifier for Ultra-Wideband Application
作者: 王柏之
郭建男
電子研究所
關鍵字: 超寬頻;低雜訊放大器;ultra-wideband;low noise amplifier
公開日期: 2003
摘要: 本篇論文主旨在於利用標準0.18um CMOS製程設計適用於超寬頻系統前端接受器之低雜訊放大器積體電路。此外,使用達靈頓對架構之窄頻低雜訊放大器亦被設計與分析。此兩顆低雜訊放大器已經由晶片製作而被驗證。 第一顆晶片在於設計與分析一適用於5-GHz頻帶無線區域網路之高增益低雜訊放大器。此放大器使用達靈頓對之兩倍截止頻率之特性來達到高增益之目的。實驗結果顯示此一放大器在6GHz頻率有著最高功率增益(S21) 15.5dB,輸入返回損耗(S11) -12 dB 以及最低雜訊指數3.5dB,此外此電路消耗之功率為13mW。 在第二顆晶片裡,適用於接收端超寬頻系統之寬頻放大器被設計與分析。我們利用負回受電阻達到寬頻之輸入阻抗匹配以及自偏壓,增益補償方法達到操作頻率範圍內之平坦增益,進而濾除操作頻率範圍外之訊號。實驗結果顯示此一放大器在3-8 GHz頻率下有著最高功率增益(S21) 9.2dB,輸入返回損耗(S11)低於 -5.8dB 以及平均雜訊指數6.1dB,此電路消耗之功率為15mW。此外,改善性能之超寬頻放大器已被製作,並且加入了可變增益之功能以增加輸入信號動態範圍。
The aim in this thesis is mainly based on the design of low noise amplifier (LNA) in the receiver path of ultra-wideband system using standard 0.18um CMOS process. Also, a narrow band LNA using Darlington pair structure is designed for 5.5-GHz frequency band. The two low noise amplifiers were verified through 2 individual chips. In the first chip, a narrow band high gain low noise amplifier using Darlington pair structure is analyzed and designed for wireless local network area (WLNA) operating at 5-GHz frequency band. We employ the double cutoff frequency property of Darlington pair to achieve high gain design. Measured data show that the amplifier achieves maximum power gain (S21) of 15.5 dB, -12 dB input return loss (S11), and minimal noise figure of 3.5 dB at the 6GHz frequency while consuming 13mW. In the second chip, a wideband amplifier (LNA), intended for use in the receiver path of an ultra-wideband (UWB) system, is analyzed and designed. We employ the techniques of negative feedback resistors to achieve broadband matching together with self-biasing, and gain compensation method to derive flat gain over the entire operating frequency band as well as filter out the signal out of band. Measured data show that the amplifier achieves maximum power gain (S21) of 9.2 dB, input return loss (S11) below -5.8 dB, and average noise figure of 6.1dB in the frequency range from 3 to 8-GHz, while consuming only 15mW. The improved and modified version in terms of the measured result from this chip has been implemented. Also, variable gain function has been added to enlarge the input dynamic range in the modified chip.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009111664
http://hdl.handle.net/11536/44257
Appears in Collections:Thesis


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