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dc.contributor.author謝建宇en_US
dc.contributor.authorHsieh, Chien-Yuen_US
dc.contributor.author莊景德en_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2015-11-26T01:05:22Z-
dc.date.available2015-11-26T01:05:22Z-
dc.date.issued2010en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079711551en_US
dc.identifier.urihttp://hdl.handle.net/11536/44252-
dc.description.abstract本論文提出了利用獨立閘極操作鰭狀場效電晶體操作在次臨界區以史密特觸發器為基礎的三種新穎的靜態隨機存取記憶體單元。這三種8T記憶體單元(IG_STs)利用獨立閘極特性鰭狀場效電晶體,前端閘極當作是推疊的電晶體;後端閘極當作是中間的節點來產生史密特觸發器內建回饋的機制。成功減少了電晶體數目以及縮小了面積,並且得到較佳的靜態雜訊邊界(SNM)值和對製程飄移及本質參數變異-線邊緣粗糙程度(Line Edge Roughness)有更佳的容忍度。 經由3D mixed-mode元件模擬器(TCAD)得知SNM值、靜止狀態漏電流值,並跟傳統6T及過去文獻上(ST1、ST2)的類似記憶體單元做比較。跟6T比較操作在0.4V時,讀取時靜態雜訊邊界(RSNM)增加了81%並且操作在更低電壓(0.15V)同時更增加了110%。根據32奈米節點的佈局規則,從實際佈局圖中得知這三種記憶體單元(IG_STs)有著比過去文獻中(ST1,ST2)更好的密度的優勢。另外記憶體單元的讀取、寫入時間、讀取時間因為同一條位元線其它非選取到記憶體細胞在讀取的同時由於其儲存的資料內容經由位元線漏電流造成讀取失敗的效應也都模擬了,此外加上溫度效應去看因漏電流的增加所導致不同的讀取時間。結果顯示出是符合操作在次臨界區域所要求的速度。 由於操作在次臨界區必須更關注於記憶體單元的穩定度,於是在本質參數變異部分我們考慮了線邊緣的粗糙程度( Gate – ,and Fin – Line Edge Roughness) 和功函數變異程度(Work Function Variability)並且利用3D mixed-mode蒙地卡羅模擬來檢驗其穩定度。此外更加上了考慮製程飄移(Leff, EOT, Wfin(Tsi,) and Hfin)而導致的變異可更系統性的來看其穩定度,結果可以得知在最差的製程飄移條件之下(FNSP),我們提出的兩種新記憶體單元仍然能滿足足夠的μ/σ的比例。zh_TW
dc.description.abstractIn this paper, we propose three novel Independently-controlled-Gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. The proposed IG_ST 8T SRAM cells utilize split-gate FinFET devices with the front-gate devices serving as the stacking devices, and the back-gate devices serving as the intermediate node conditioning devices to provide built-in feedback mechanism for Schmitt Trigger action, thus reducing the cell transistor count/area and achieving improved SNM and better tolerance to process variation and local random variation (LER). 3D mixed-mode simulations are used to evaluate the SNM, and Standby leakage of proposed cells, and results are compared with the standard 6T cells and previously reported 10T Schmitt Trigger sub-threshold SRAM cells (ST1 and ST2). Compared with the conventional tied-gate 6T cell, the proposed IG_ST SRAM cells demonstrate 1.81X and 2.11X higher nominal RSNM at VCS=0.4V and 0.15V, respectively. The cell layouts and areas are assessed based on scaled ground rules from 32 nm node, and the density advantage over previously reported 10T Schmitt Trigger sub-threshold SRAM cells are illustrated. The cell AC performance (Read access time, Write time, and Read access time versus the number of cells per bit-line) and temperature dependence are evaluated, and shown to be adequate for the intended sub-threshold applications. Stability is a critical concern in sub-threshold region, so we consider Gate –, and Fin – Line Edge Roughness, and Work Function Variability using 3D mixed-mode Monte Carlo simulations to investigate its stability. Moreover, process variations (Leff, EOT, Wfin(Tsi,), and Hfin) are performed for systematic variation concern. Our results indicate that even at the worst corner (FNSP), two of the proposed cells can provide sufficient margin of μ/σ ratio.en_US
dc.language.isoen_USen_US
dc.subject靜態隨機存取記憶體zh_TW
dc.subject次臨界區域zh_TW
dc.subject鰭狀場效電晶體zh_TW
dc.subject抗製程變異zh_TW
dc.subjectSRAMen_US
dc.subjectSub-thresholden_US
dc.subjectFinFETen_US
dc.subjectProcess Toleranceen_US
dc.title史密特觸發器為基礎操作在次臨界區以獨立閘極控制場效鰭狀電晶體之靜態隨機存取記憶體zh_TW
dc.titleIndependently-Controlled-Gate FinFET Schmitt Trigger Sub-threshold SRAMsen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis


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