A Study of the Fabrication and Characteristics of Poly-Ge Thin-Film Transistors with Raised Source/Drain
|摘要:||在本篇論文中，我們製作並探討含有矽化鎳或多晶矽之昇起式源/汲極的多晶鍺電晶體特性。在製作元件過程中，利用低溫500℃的固相結晶法形成多晶鍺通道。而由於缺陷出現於元件氧化層與通道的介面之間，因此初完成的元件特性尚未能穩定。但在經過多次的量測之後，元件表現出較好的次臨界擺幅特性(subthreshold swing)，並達到等級約為105的開關電流比(Ion/Ioff ratio)。然而，透過固相結晶法形成的多晶鍺，其晶粒尺寸偏小，使得臨界電壓的範圍廣且差異幅度從7.75V至10.75V。
另外，我們認為昇起式源/汲極區域的鎳化矽與多晶矽於固相結晶時為多晶鍺通道的種晶層(seeding layer)。進一步萃取昇起式多晶矽與鎳化矽源/汲極區域的電阻值，分別為0.575MΩ與0.490 MΩ。除此之外，由於種晶層對非晶鍺的結晶影響，多晶鍺通道的結晶度為非均勻並與所處的位置相關。
最後，我們討論不同的汲極對源極的電壓對電流電壓特性。即使在通道較長的尺寸下，我們發現汲極引致晶粒能障下降(drain–induced grain barrier lowering, DIGBL)效應應為在不同的汲-源電壓下導致電流變化的主要原因。|
In this thesis, we have fabricated and characterized poly-Ge TFT devices with raised NiSi or poly-Si source/drain (S/D). The poly-Ge channel was formed with solid-phase crystallization (SPC) method at a lower temperature (500℃). The fresh device characteristics are not stable due to the defects presenting at or near the channel/oxide interface. After several repeated measurements are executed, superior device performance with smaller S.S. and Ion/Ioff ratio of about 105 is achieved. However, owing to the small grain size formed by SPC treatment, the threshold voltage range is wide and varies from 7.75 V to 10.75 V. The poly-Si and NiSi are expected to serve as the seeding layer for crystallization during the SPC treatment. Furthermore, we also extracted the RSD for raised poly-Si and NiSi S/D and found to be 0.575 MΩ and 0.490 MΩ, respectively. Moreover, we also showed that the crystallinity in the channel is non-uniform and location dependent, owing to the action of the seeding layer in crystallizing the α-Ge. Finally, the ID-VG characteristics under different VDS also have been investigated. Even when the channel length is long, we also found that the DIGBL effect is likely the main cause for the significant shift in ID as VDS is varied.
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