標題: 多晶鍺奈米線薄膜電晶體與無接面多晶矽奈米線場效電晶體製作與特性分析
A Study on the Fabrication and Characterization of Poly-Ge NWTFTs and Junctionless Poly-Si NWFETs
作者: 劉禹伶
Liou, Yu-Ling
林鴻志
黃調元
Lin, Horng-Chih
Huang, Tiao-Yuan
電子研究所
關鍵字: 多晶鍺;奈米線;薄膜電晶體;多晶矽;無接面;poly Germanium;nanowire;thin film transistor;poly Silicon;junctionless
公開日期: 2010
摘要: 在本論文中,我們製作並研究兩種新穎的奈米線元件,多晶鍺奈米線薄膜電晶體(poly-Ge NWTFTs)與無接面多晶矽奈米線場效電晶體(JL poly-Si NWFETs)。多晶鍺奈米線薄膜電晶體採用一種先進的邊襯蝕刻技術形成奈米線,並利用固相結晶法(SPC)將非晶鍺轉換為多晶鍺。利用多閘極(multiple-gated)的結構,開關電流比可以增加至10^4,次臨界擺幅可以改善至0.64 V/dec。此外,我們也比較了具有獨立雙閘極(independent double-gated)的多晶鍺奈米線電晶體在各種模式操作時的特性。 無接面多晶矽奈米線場效電晶體(JL poly-Si NWFETs)利用一種簡單的方法,同時形成源/汲極與通道,且不需要離子佈植即可完成。在特性表現方面,無接面多晶矽奈米線場效電晶體擁有較佳的操作電流與更低的串連電阻。此外,增強型(IM)奈米線場效電晶體在特定操作條件下展現出低於60m V/dec的次臨界擺幅。
In this thesis, two kinds of nanowire devices, namely, poly-Ge nanowire thin film transistors (NWTFTs) and junctionless (JL) poly-Si nanowire field effect transistors (NWFETs) were fabricated and investigated. Poly-Ge NWTFTs were realized with a novel approach by adopting the sidewall spacer etching technique for NW channel formation. Solid phase crystallization (SPC) was utilized to transform amorphous Ge (α-Ge) to poly-Ge. By adopting multiple-gated structure, ON/OFF current ratio is increased to 104 and subthreshold swing (S.S.) is improved to 0.64V/dec. Besides, poly-Ge NWTFTs with independent double-gated (DG) configuration are characterized and compared. Each gate can be biased independently to manipulate the device. JL poly-Si NWFETs were fabricated in a simplified manner duo to the fact that the source/drain (S/D) and channel was formed simultaneously without implantation. JL devices show better on-state performance and lower series resistance. On the other hand, the inversion mode (IM) NWFETs present ultra-low S.S. lower than 60mV/dec under specific operation conditions.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079711540
http://hdl.handle.net/11536/44241
Appears in Collections:Thesis


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