標題: 以複晶矽薄膜電晶體製作新穎高速電荷儲存式記憶體之研究
Study on the Novel High Speed Charge Trapping Memory Devices with Poly-Si TFTs
作者: 劉晏廷
Liu, Yen-Ting
鄭晃忠
電子研究所
關鍵字: 電荷儲存式記憶體;複晶矽薄膜電晶體;角隅;高介電材質;真空;Charge Trapping Memory Device;Poly-Si TFT;Corner;high-k;Vacuum
公開日期: 2010
摘要: 由於傳統的電荷儲存式記憶體在寫入和抹除的速度上,比起懸浮閘極式記憶體有一段差距,因此,近年來許多人致力於進行改善電荷儲存式記憶體寫入和抹除速度的研究。然而,大多數能改善寫入和抹除速度的方法,同時也造成了一些可靠度不佳的問題。在這篇論文,我們分成兩個主題進行研究。 第一個,在SONOS之電荷儲存式記憶體架構上,以FinFET、Omega Gate與GAA之結構探討其角隅效應。利用角隅這種尖銳的幾何結構能提升在穿隧層的電場並降低在阻擋層的電場,進而大大地加快寫入速度。因此,以GAA結構設計的SONOS記憶體展現出最高的寫入效率,也進一步證明了有越多角隅的SONOS記憶體擁有越快的寫入效率。 第二個,在SONOS之架構上,以真空取代穿隧氧化層,並以高介電常數介電質作為阻擋層,設計成新穎的TANVAS和THNVAS記憶體元件。採用Al2O3 或HfO2作為阻擋層,或使用真空作為穿隧層,皆能增加在穿隧層的電場並降低在阻擋層的電場,進而促使寫入和抹除速度能顯著的提升。因此,TANVAS和THNVAS比起TANOS和THNOS有較高的寫入和抹除效率。對使用oxide作為穿隧層的記憶體元件來說,在經過幾個寫入/抹除週期後,oxide穿隧層很容易受到外力的傷害而產生缺陷,使用真空作為穿隧層則能克服這項問題,所以TANVAS記憶體元件展現出良好的元件耐久度特性。在電荷保存能力方面,由於oxide穿隧層中的traps和HfO2阻擋層的低能障高度皆有助於載子的流動,容易形成漏電路徑,因此THNVAS和TANOS無法長時間將載子保存於電荷儲存層內。TANVAS避開了這些問題,所以展現出良好的資料保存性。 在經過對電性的探討和分析後,我們得到一些令人滿意的結果。我們的研究能顯著地提升寫入和抹除的速度,同時還能維持良好的元件耐久度和資料保存性。這在未來的高密度電路和系統面板具有相當大的發展潛力。
In recent years, many researchers have drawn attention to improve the program/erase efficiency of charge trapping memory devices owing to the program/erase efficiency of conventional charge trapping memory devices is lower than that of floating gate memory devices. However, most methods of improving the program/erase efficiency resulted in poor reliability issues. In this thesis, our investigation has been classified into two topics. At first, for Poly-Si TFT SONOS memory devices, we have proposed a FinFET structure, an omega gate structure, and a GAA structure to investigate the corner effect. Since the sharp corner geometric will increase electric field in the tunneling layer and decrease electric field in the blocking layer, the program speed can be enhanced greatly. Consequently, the SONOS memory device with a GAA structure exhibits the highest program efficiency and it proves that SONOS memory devices with more corners will enhance program efficiency. On the other hand, we have proposed novel high speed Poly-Si TFT TANVAS and THNVAS memory devices with high-k blocking layer and vacuum tunneling layer. Utilizing high-k materials, such as Al2O3 and HfO2, as blocking layer or using low-k materials, like vacuum, as tunneling layer can increase electric field in the tunneling layer and decrease electric field in the blocking layer. Based on this field enhanced scheme, the proposed memory devices reveal excellent memory performance. It is shown obviously that the TANVAS and THNVAS memory devices have higher program/erase efficiency than the TANOS and THNOS memory devices. Furthermore, the conventional SiO2 tunneling layer is always suffered from damage after program/erase cycles. Using vacuum tunneling layer can overcome this obstacle so that the TANVAS memory device exhibits better endurance characteristics. Due to the traps in oxide tunneling layer and lower conduction band offset in HfO2 blocking layer will provide leakage paths for charges, the TANOS and THNVAS memory devices are not able to preserve stored charges for a long time. The TANVAS memory device can avoid these problems and presents great retention characteristics. Through investigating and analyzing the electrical characteristics, we obtain some satisfying results. The program/erase efficiency of proposed memory device is enhanced remarkably, and exhibits great endurance and retention characteristics. They are very promising for future applications in high density circuits and SOP.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079711506
http://hdl.handle.net/11536/44205
Appears in Collections:Thesis


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