標題: MPEG-4先進音訊編碼在DSP/FPGA平台上的實現與最佳化
MPEG-4 AAC implementation and optimization on DSP/FPGA
作者: 曾建統
Chien-Tung Tseng
杭學鳴
Hsueh-Ming Hang
電子研究所
關鍵字: 先進音訊編碼;MPEG;AAC;IMDCT
公開日期: 2003
摘要: MPEG-4 先進音訊編碼(AAC)是由ISO/IEC MPEG所制訂的一套非常有效率的音訊壓縮編碼標準。在本篇論文當中,我們首先統計MPEG-4先進音訊編碼在DSP上的執行情況,發現霍夫曼解碼(Huffman decoding)和反修正離散餘弦轉換(IMDCT)所需要的時脈週期總數為最多,因為針對反修正離散餘弦轉換在DSP上的實現作最佳化,同時我們也希望利用FPGA來克服用DSP執行的瓶頸部分,所以將霍夫曼解碼以及反修正離散餘弦轉換的一部份反快速傅立葉轉換(IFFT)放到FPGA實現。在DSP實現方面,我們針對DSP的架構使用運算量更少的演算法,使用適合DSP處理的資料型態,並使用TI DSP特殊指令來改寫程式,大幅提高其執行效率,這個部分大約增加了503倍的速度。在FPGA實現方面,我們設計針對霍夫曼解碼以及反快速傅立葉轉換的架構,並針對硬體架構設計來作調整,使其運算效能提高,同時兼顧減少使用面積的考量。霍夫曼解碼大約比DSP的版本增加了56倍的速度,反快速傅立葉轉換大約較DSP最快的版本增加了4倍的速度。最後並考慮DSP和FPGA設計之間的溝通問題。
MPEG-4 AAC (Advanced Audio Coding) is an efficient audio coding standard. It is defined by the MPEG (Moving Pictures Experts Groups) committee, which is one of ISO (International Standard Organization) working groups. In this thesis, we first analyze the computational complexity of MPEG-4 AAC decoder program. We found that the Huffman decoding and the IMDCT (inverse modified discrete cosine transform) require the most clock cycles to execute on DSP. Hence, we optimize the IMDCT codes on DSP. In addition, we use FPGA to remove the bottleneck in DSP execution. Thus, we implement the Huffman decoding and the inverse fast Fourier transform), which is a part of IMDCT, on FPGA. In order to speed up the AAC decoder on DSP, we need to choose appropriate algorithms for DSP implementation. Thus, appropriate data types are chosen to present the data. Furthermore, we use the TI (Texas Instruments) DSP intrinsic functions to increase the DSP execution efficiency. The modified version of IMDCT is about 503 times faster than the original version. For the FPGA implementation, we adopt and modify the existing architectures for Huffman decoding and 512-point IFFT. In addition, we use VLSI design techniques to improve the performance and reduce the chip area in FPGA implementation. The FPGA implementation of Huffman decoding and 512-point IFFT is about 56 and 4 times faster than the corresponding DSP implementations, respectively. Also, in this project, we design and implement the communication interface between DSP and FPGA.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009111656
http://hdl.handle.net/11536/44179
Appears in Collections:Thesis


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