Study of the T-Shaped Gate Low Temperature Polycrystalline Silicon Thin Film Transistors with the In-situ Vacuum Gaps
Polycrystalline silicon thin film transistors (poly-Si TFTs) has been widely used as the pixel switching elements in active matrix addressed flat panel display due to their higher carrier mobility compared with a-Si TFTs. However, the large off-state leakage current and device instability caused by the high electric field near the drain junction impede the usage of poly-Si in high performance circuit applications. In order to alleviate the high electric field near the drain junction, lots drain-field-relief structures have been proposed. However, most of them not only require complicated fabrication process but also increase the manufacturing cost. In this thesis, we proposed a high drain-field-relief efficiency T-shaped gate (T-Gate) poly-Si TFTs by using a simple fabrication sequence. Specifically, the T-Gate structure does not need additional photolithography step nor ion implantation step, it only requires a simple side-etching process by wet-etching method. Besides, vacuum gaps served as the drain-field-relief element were in-situ embedded under the T-Gate electrode during the SiH4-based passivation process. The simulations were carried out to evaluate the electric field effect on the T-Gate structure. Following that, the electrical characteristics including transfer characteristics, output characteristics, breakdown characteristics, symmetry characteristics and reliability issues were all investigated. Results of this study showed that the T-Gate TFTs exhibit much lower off-state leakage current, good on/off current ratio, better kink-effect immunity and better reliabilities.
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