標題: IEEE 802.16a標準之前向誤差改正編碼於數位訊號處理器平台上之實現與最佳化
DSP Implementation and Optimization of the Forward Error Correction Scheme in IEEE 802.16a Standard
作者: 李仰哲
Young-Tse Lee
杭學鳴
Dr. Hsueh-Ming Hang
電子研究所
關鍵字: 前向誤差改正編碼;最佳化;FEC;802.16a;Optimization
公開日期: 2003
摘要: 在IEEE 802.16a無線通訊標準中,於系統的傳送端與接收端都分別訂定了前向誤差改正編碼的機制,藉此減低通訊頻道中雜訊失真的影響。本篇論文的重點在於,實現標準所訂定的前向誤差改正編碼系統於數位訊號處理器(DSP)平台上,並且針對DSP平台(此平台包含DSP與FPGA)的特性以及前向誤差改正編碼的演算法進行程式的改進。在此篇論文中、我們將標準中制訂的四個必備的前向誤差改正編碼系統,實現在以德州儀器公司所發展的DSP為核心的平台上。由於我們關注的重點在於程式的執行效率,因此在簡短地介紹過我們所使用的前向誤差改正編碼的演算法以及DSP平台的架構與軟體最佳化技巧後,我們將逐步地闡述如何在DSP平台上最佳化我們的程式。最後我們可以在程式執行效率上達到明顯的進步,前向誤差改正編碼的編碼器部分,經過改進後,於DSP模擬器上、可以達到每秒7984K位元的處理速度,而解碼器的部分可以達到每秒750K位元的處理速度。此外、針對我們所使用的數位處理器平台上內建的Xilinx FPGA,我們也做了兩項模擬來評估在Viterbi解碼器最佳化中的瓶頸:”加-比-選”(ACS)單元在FPGA上的處理效率。受限於DSP與FPGA之間的傳輸頻寬,原本在FPGA上的處理速度應為每秒45M 64狀態的ACS單元,實際上僅能達到每秒32M 64狀態的處理速度。
In the IEEE 802.16a wireless communication standard, a Forward Error Correction (FEC) mechanism is presented at both the transmitter and the receiver sides to reduce the noisy channel effect. The focus of this thesis is DSP implementation of the FEC scheme defined in IEEE 802.16a standard and modifying FEC algorithms to match the architecture of DSP and FPGA platforms. We have implemented four required FEC schemes defined in the standard on the Texas Instruments (TI) TMS320C6416 digital signal processor (DSP). After a brief review of the algorithms, we describe the DSP hardware architecture and its software optimization techniques. We then explain how we optimize the FEC programs on the DSP platform step by step since the speed performance is our major concern. Finally, we achieve a significant improvement on the speed performance. At the end, the improved FEC encoder can achieve a data processing rate of 7984 Kbits/sec and the improved FEC decoder can achieve a processing rate of 750 Kbits/sec on the TI C64xx DSP simulator. Furthermore, we have done two simulations to evaluate the data processing rate of the Add-Compare-Select (ACS) unit implemented on the Xilinx FPGA since the ACS unit is the speed bottleneck of the Viterbi decoder. Due to the constraint on transmission bandwidth between DSP and FPGA, the processing rate of the ACS unit on FPGA can only approach 32M (64 states/sec), while the actual processing rate on FPGA is 45M (64 states/sec).
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009111602
http://hdl.handle.net/11536/43657
Appears in Collections:Thesis


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