標題: 應用於超高速傳輸多天線系統(MIMO-OFDM)頻域上之高時脈誤差容忍時間同步器
Frequency-Domain Timing Synchronizer with Wide Clock Offset Tolerance in Very-High-Throughput MIMO-OFDM Systems
作者: 陳名瑜
Chen, Ming-Yu
張立平
Chang, Li-Pin
多媒體工程研究所
關鍵字: 時間同步;取樣偏移;正交分頻;Timing Synchronization;Sampling Clock Offset;OFDM
公開日期: 2008
摘要: 隨著無線通訊技術的快速發展,超高速傳輸系統已成為新一代無線通訊系統的發展核心,然而高速傳輸需要更快的取樣頻率,這將使得「大量取樣頻率偏移」此問題發生的機率增加,這將造成訊號嚴重的衰減。因此,本論文致力於研究在2048-FFT下超高速多天線正交分頻多工系統中(MIMO OFDM),頻率域上的時間同步器,並以調節取樣相位的方式補償取樣頻脈誤差,達到同步取樣的目的。 本論文所提出的演算法,主要應用在 IEEE 所制定的無線區域網路標準 IEEE 802.11n,藉由利用封包前端格式固定的preambles,針對其彼此間的相關性對取樣頻率誤差作估計以及補償。此演算法中,總共使用六個preambles。在高斯雜訊及多路徑衰減的情形下,以封包錯誤率(PER)小於8%為標準,效能可以達到容忍-30000~40000-ppm的時脈偏移影響。
Due to the explosive growth demand for wireless communication, the next-generation wireless communication systems are expected to provide high-speed and high-throughput. However, high-speed transmission needs high sampling rate, which would cause wide sam-pling clock offset. Based on phase adjustment, this work investigates a frequency-domain timing synchronizer to perform coherent sampling for 2048-FFT Multiple-Input Mul-tiple-Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) timing recov-ery. In the proposed algorithm, we use a multiphase all-digital clock management (ADCM) which can generate more than 32 phases over GHz without phase-locked or delay-locked loops to adjust sampling phases and utilize the correlation between short preambles to es-timation the sampling phase error. It can perform the sampling clock synchronization effi-ciently and quickly. Performance evaluation indicates that the proposed timing synchronizer can tolerate -30000 ~ 40000ppm sampling clock offsets with 0.2db SNR losses at 8% PER in frequency-selective fading. Hence, this scheme involves a little overhead to ensure fast recovery and wide offset tolerance for OFDM packet transmissions.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079657551
http://hdl.handle.net/11536/43559
Appears in Collections:Thesis


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  1. 755101.pdf