Characterization of Polysilicon Thin Film Transistors with Asymmetric Source/Drain Implantation and with Sidewall Floating Gate structure
|關鍵字:||薄膜電晶體;漏電;浮閘;記憶體;薄膜;TFT;thin film;floating gate;memory;leakage|
在論文中第四章的部份，我們也提出一個新的元件結構稱之為側壁浮閘結構之複晶矽薄膜電晶體。利用自我對準的方式在閘極兩端側壁製備浮閘結構，並利用此浮閘受閘極電廠感應的效果來抑制元件高關閉電流。此外，浮閘再寫入╱抹除動作之後並可以用來記憶載子使元件切換電壓改變。也就是說，此元件具備電子式抹除可寫入唯讀記憶體(Electrical Erasable Programmable Read Only Memory, PROM)特性。多晶矽薄膜電晶體的一大優點就是未來可以在主動式液晶面板上製作積體電路，而記憶體結構則是可以用來儲存影像的單元。此ㄧ側壁浮閘結構具有自我對準不需多加光罩的優點與以往被提出的多晶矽薄膜電晶體記憶體比較更具微縮與可用性。|
Polycrystalline Silicon Thin-Film Transisitors have been proposed and investigated in recent years since its high driving current and mobility. However, there is some disadvantages in polycrystalline thin-film transistors. One of the most important is the channel region formed by poly grain, and the poly grains have a lot of grain boundary defects. Those defects degrade TFTs’ on-state driving current and mobility. Moreover, grain boundary defects enhance high off-state leakage whenever devices are biased at off-state. The use of conventional polycrystalline thin-film transistors for active matrix liquid crystalline display was hampered by anomalous leakage current. For past decade, many fabrication ways and device structures had been proposed such as plasma treatment, lightly-doped-drain TFTs and field induced drain TFTs. However, these structure need either more process or additional mask than conventional TFTs. And more process or additional mask means higher fabrication costs and time as well as misalignment. In this thesis, we have investigated and proposed two new poly-Si TFTs structures. In chapter three, we investigate a newstructure named polysilicon thin-film transistors with assymetric source/drain implantation which was fabricated by simply tilt the implant angle. The asymmetric implantation at source/drain forms lightly-doped-drain region beside drain side and it is used to suppress leakage current which results from the high drain side electric field. In this new structure, there is no additional mask needed and the fabrication process is as easy as conventional ones. In the chapter four, we investigated and proposed a new poly-Si TFTs named polysilicon thin-film transistors with sidewall floating gate structure. By self-aligned, two floating gate beside gate electrode are formed. Sidewall floating gate was electrical coupled by the main gate and used to suppress the high off-state current. After program/erase, sidewall polysilicon was able to record electrons such as floating gate in memory cell. In other words, it works as electrical erasable programmable read only memory (EEPROM). One of the important applications to polycrystalline thin-film transistors is used to fabricate system on panel (SOP). Electrical Erasable PROM (EEPROM) devices are very popular for applications such as programmable logic and high density memories. And the realization of LSI circuits and memories for image storage on AMLCD panel was led by polycrystalline silicon TFTs EEPROM’s process. This self-aligned thin-film transistors with sidewall floating gate is higher ability of scale down and applicable.
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