標題: 非對稱源極/汲極離子佈植及側壁浮閘結構之複晶矽薄膜電晶體特性
Characterization of Polysilicon Thin Film Transistors with Asymmetric Source/Drain Implantation and with Sidewall Floating Gate structure
作者: 林余俊
Yu-Juen Lin
雷添福
Tan-Fu Lei
電子研究所
關鍵字: 薄膜電晶體;漏電;浮閘;記憶體;薄膜;TFT;thin film;floating gate;memory;leakage
公開日期: 2003
摘要: 多晶矽薄膜電晶體近年來受到廣泛開發與研究乃因其與非晶矽薄膜電晶體比較有高驅動電流,高載子遷移率等特性。然而低溫複晶矽並非完美無暇,其通道組成的複晶矽結構中含有許多缺陷,而這些結構缺陷會對電晶體的導通電流、載子遷移率造成劣化的現象。此外,這些缺陷也同時形成了漏電路徑,對元件操作在關閉狀態時仍有高關閉電流。這阻礙了多晶矽薄膜電晶體在主動式矩陣液晶顯示器上的應用。過去幾年來已經有許多改善多晶矽薄膜電晶體的漏電現象的論文被發表,諸如電漿處理、淡摻雜汲極結構和場感應汲極結構等等。然而這些結構不是需要比傳統製程多的步驟就是需要多一道光罩來達成結構的製備,製程成本、處理時間和對準錯誤等問題隨著接踵而至。 在本論文中,吾人致力於多晶矽薄膜電晶體的特性研究與新元件結構的開發。在本論文第三章中,我們提出一個相當簡單的結構,利用傾角的技巧以元件閘極當屏蔽對元件做不對稱離子佈植。在源極╱汲極回火活化後,即自然於一端產生輕摻雜區域並以此端當汲極,利用輕摻雜區域抑制漏電。在此一新結構中,僅需簡單的製程流程並且無需多加任一道光罩即可達成。在這個基礎上,我們相信這是一個相當有價值的新元件結構。 在論文中第四章的部份,我們也提出一個新的元件結構稱之為側壁浮閘結構之複晶矽薄膜電晶體。利用自我對準的方式在閘極兩端側壁製備浮閘結構,並利用此浮閘受閘極電廠感應的效果來抑制元件高關閉電流。此外,浮閘再寫入╱抹除動作之後並可以用來記憶載子使元件切換電壓改變。也就是說,此元件具備電子式抹除可寫入唯讀記憶體(Electrical Erasable Programmable Read Only Memory, PROM)特性。多晶矽薄膜電晶體的一大優點就是未來可以在主動式液晶面板上製作積體電路,而記憶體結構則是可以用來儲存影像的單元。此ㄧ側壁浮閘結構具有自我對準不需多加光罩的優點與以往被提出的多晶矽薄膜電晶體記憶體比較更具微縮與可用性。
Polycrystalline Silicon Thin-Film Transisitors have been proposed and investigated in recent years since its high driving current and mobility. However, there is some disadvantages in polycrystalline thin-film transistors. One of the most important is the channel region formed by poly grain, and the poly grains have a lot of grain boundary defects. Those defects degrade TFTs’ on-state driving current and mobility. Moreover, grain boundary defects enhance high off-state leakage whenever devices are biased at off-state. The use of conventional polycrystalline thin-film transistors for active matrix liquid crystalline display was hampered by anomalous leakage current. For past decade, many fabrication ways and device structures had been proposed such as plasma treatment, lightly-doped-drain TFTs and field induced drain TFTs. However, these structure need either more process or additional mask than conventional TFTs. And more process or additional mask means higher fabrication costs and time as well as misalignment. In this thesis, we have investigated and proposed two new poly-Si TFTs structures. In chapter three, we investigate a newstructure named polysilicon thin-film transistors with assymetric source/drain implantation which was fabricated by simply tilt the implant angle. The asymmetric implantation at source/drain forms lightly-doped-drain region beside drain side and it is used to suppress leakage current which results from the high drain side electric field. In this new structure, there is no additional mask needed and the fabrication process is as easy as conventional ones. In the chapter four, we investigated and proposed a new poly-Si TFTs named polysilicon thin-film transistors with sidewall floating gate structure. By self-aligned, two floating gate beside gate electrode are formed. Sidewall floating gate was electrical coupled by the main gate and used to suppress the high off-state current. After program/erase, sidewall polysilicon was able to record electrons such as floating gate in memory cell. In other words, it works as electrical erasable programmable read only memory (EEPROM). One of the important applications to polycrystalline thin-film transistors is used to fabricate system on panel (SOP). Electrical Erasable PROM (EEPROM) devices are very popular for applications such as programmable logic and high density memories. And the realization of LSI circuits and memories for image storage on AMLCD panel was led by polycrystalline silicon TFTs EEPROM’s process. This self-aligned thin-film transistors with sidewall floating gate is higher ability of scale down and applicable.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009111571
http://hdl.handle.net/11536/43357
Appears in Collections:Thesis


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