標題: 先進互補式金氧半元件的閘極層厚度1nm範圍下之低漏電電荷幫浦量測技術
Low Leakage Charge Pumping Measurement Techniques for Advanced CMOS with Gate Oxide in the 1nm Range
作者: 馮信榮
Feng Hsin Jung
莊紹勳
Steve S. Chung
電子研究所
關鍵字: 電荷幫浦;閘極氧化層;低漏電;中和;界面缺陷;氧化層缺陷;Charge Pumping;gate oxide;low leakage current;neutralization;interface trap;oxide trap
公開日期: 2003
摘要: 美國ITRS (SIA) Roadmap指出,到了西元2005年元件通道長度將進展到75nm,而閘氧化層厚度將縮為10~15Å。因此,如何觀察高穿隧漏電的10~15Å氧化層對下一代的CMOS技術是一大關鍵,尤其是觀察氧化層中界面缺陷和氧化層缺陷電荷的可靠性量測技術,相當欠缺。截至目前,有幾種量測氧化層可靠性的方法,如DCIV, Gated-Diode (GD)、charge pumping(CP)等。然而,當超薄氧化層厚度低到20 Å,它們受限於量測時導致大量的閘極穿隧漏電流(gate leakage tunneling current)而產生嚴重誤差。 這篇論文主要的重點在於發展一套對於超薄氧化層的90nm CMOS元件之新的量測技術。我們已經成功的發展出這套結合 IFCP方法和分離界面缺陷以及氧化層缺陷電荷的三步驟電荷中和的嶄新量測技術。 在這裡所使用的量測樣本的氧化層是經由DPN處理的製程。氧化層厚度有14 Å 和16Å而且每種厚度分別都包含三種不同的氮含量。我們以介面缺陷和氧化層缺陷電荷的通道方向分佈情形來觀察不同厚度以及不同氮含量的CMOS元件,在熱載子和NBTI影響下的可靠性比較。在短通道的情形下,元件衰退的主要偏壓條件從IB,max轉換到VG= VD。在VG= VD的偏壓情形下,有高含量的氮以及較薄的nMOSFET元件有較好的可靠性,而有低含量的氮和較厚的pMOSFET元件有較好的可靠性。此外,在NBTI的影響下,我們發現氮含量對於元件的可靠度扮演一個重要的角色。從界面缺陷的分步情形,pMOSFET在NBTI影響下,擁有較高的氮含量會導致最差的元件衰退狀況。此外,我們也發現pMOSFET在NBTI-like影響下會在高溫下增加熱載子對元件的影響,而且低含量的氮會有最佳的可靠度。
As device scaling continues, the sub-100nm CMOS device needs a gate oxide thickness in the range of 10-15Å and with 75nm gate length in 2005, as predicted from the SIA roadmap. How to monitor oxide quality for ultra-thin gate oxide with tunneling leakage current is crucial for the next generation CMOS technology, in particular the monitoring of interface traps (Nit) and oxide trapped charges (Qot) in the gate oxide. So far, various gate oxide reliability diagnostic tools, such as DCIV, GD(Gated-Diode), CP(Charge-Pumping) etc. have been employed for such a purpose. For ultra-thin gate oxide down to below 20 Å, the above methods are limited by the tunneling leakage through the gate oxide during the measurement since direct tunneling exists. This thesis has been focused on developing new techniques for the measurement of ultra-thin gate oxide 90nm CMOS devices. We have successfully developed new method, combing IFCP method to remove direct tunneling current and an improved three-steps neutralization to separate Nit and Qot measurement technique. The test sample in this work is prepared based on the DPN gate oxide process. The EOT of gate oxide thickness are 14Å and 16 Å, which have three different nitrogen concentrations, respectively. We compare the oxide thickness dependence and concentration of plasma nitridation of CMOS device under HC stress and NBTI stress from the lateral profiling of interface traps and oxide traps. In short channel length, the dominate stress condition of device degradation switched from IB,max to VG= VD. Under VG= VD stress condition, the gate oxide with higher plasma nitrogen density and thinner thickness has better reliability for nMOSFET and the gate oxide with lower plasma nitrogen density and thicker thickness has better reliability for pMOSFET. Moreover, we found that nitrogen played an important role in device reliability under NBTI stress. From the result of the distribution for interface traps, we know that the highest nitrogen in oxide has worst case device degradation under NBTI stress for pMOSFET. In addition, we have seen that NBTI-like stress enhances HC effect at high temperature and the lowest nitrogen content has the best reliability in pMOSFET.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009111540
http://hdl.handle.net/11536/43024
Appears in Collections:Thesis


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