標題: A NEW GENERAL-METHOD TO MODEL SIGNAL TIMING OF E D NMOS LOGIC
作者: WU, CY
LIN, YT
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-十月-1989
URI: http://hdl.handle.net/11536/4292
ISSN: 0098-9886
期刊: INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Volume: 17
Issue: 4
起始頁: 447
結束頁: 464
顯示於類別:期刊論文


文件中的檔案:

  1. A1989AV69100006.pdf