Full metadata record
DC FieldValueLanguage
dc.contributor.authorYANG, YHen_US
dc.contributor.authorWU, CYen_US
dc.date.accessioned2014-12-08T15:05:45Z-
dc.date.available2014-12-08T15:05:45Z-
dc.date.issued1989-10-01en_US
dc.identifier.issn0956-3768en_US
dc.identifier.urihttp://hdl.handle.net/11536/4288-
dc.language.isoen_USen_US
dc.titleANALYSIS AND MODELING OF INITIAL DELAY TIME AND ITS IMPACT ON PROPAGATION DELAY OF CMOS LOGIC GATESen_US
dc.typeArticleen_US
dc.identifier.journalIEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMSen_US
dc.citation.volume136en_US
dc.citation.issue5en_US
dc.citation.spage245en_US
dc.citation.epage254en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:A1989AV51700003-
dc.citation.woscount1-
Appears in Collections:Articles


Files in This Item:

  1. A1989AV51700003.pdf