Title: 使用矽製程蕭基二極體混頻器之60GHz單/雙次降頻接收機與應用於WLAN的單壓操作pHEMT低雜訊放大器
60-GHz Single/Dual Conversion Receivers Using Silicon Schottky Diode Mixers and WLAN Single-Voltage-Supply pHEMT LNAs
Authors: 王大維
Wang, Tai-Wei
Meng, Chin-Chun
Keywords: 接收機;雙次降頻器;二極體混頻器;蕭基二極體;低雜訊放大器;Receiver;Dual Conversion;Diode Mixer;Schottky Diode;LNA
Issue Date: 2008
Abstract: 本篇論文主要分為兩個主題。其一,以TSMC 0.18μm CMOS及TSMC 0.35μm SiGe BiCMOS製程將馬爾尚巴倫、鼠徑分合波器、一對二變壓器等傳統微波被動元件整合到矽晶片上,並實作出一百八十度單平衡式混頻器、環型雙平衡式混頻器、星型三平衡式混頻器等各種二極體混頻器特殊結構,並提出60GHz雙次降頻器的接收機解決方案,第一級降頻為蕭基二極體混頻器,中間級加入了低雜訊緩衝級,第二次降頻採用了電阻式混頻器,正交中頻訊號經由寬頻緩衝級輸出。 其二,是以WIN 0.15 PHEMT製程來實作單壓操作的低雜訊放大器。共設計了工作頻率在2.4~5.9GHz及4.9~5.9GHz的兩個低雜訊放大器電路。
This thesis is divided into two parts. The first part we choose TSMC 0.18μm CMOS and TSMC 0.35μm SiGe BiCMOS technology to implement traditional microwave component such as marchard balun, rat-race hybrid coupler, and tri-filar on silicon substrate chip. 180 degree single-balanced mixer, double-balanced ring mixer, and triply-balanced star mixer are implemented in this thesis. We also propose the 60GHz dual down-converter solution. Schottky barrier diode mixer is adopted at first down-converter, and a low noise buffer is added to the inter-stage. Second down-converter is a resistive mixer with quarture LO signal. The output orthogonal IF signal is through the wide-band buffer. In the second part, the low noise amplifier with single power supply is implemented with WIN 0.15um pHEMT technology. We design two kinds circuit at different frequency, which one is 2.4 to 5.9GHz and another one is 4.9 to 5.9GHz.
Appears in Collections:Thesis

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