標題: 操作在次臨界區域且使用拔靴帶式中繼器之超低功率晶片內部匯流排電路設計
An Ultra-Low Power Subthreshold On-Chip Bus Design with Bootstrapped Repeater Insertion
作者: 張家齊
Chang, Chia-Chi
蘇朝琴
Su, Chau-Chin
電控工程研究所
關鍵字: 晶片內部匯流排;拔靴帶式電路;次臨界區域;置入中繼器;超低功率消耗;on-chip bus;bootstrapped circuits;subthreshold region;repeater insertion;ultra-low power consumption
公開日期: 2010
摘要: 本論文提出一個置入了拔靴帶式中繼器的超低功率晶片內部匯流排系統,工作電壓小於電晶體的門檻電壓,大幅減少了電路的功率消耗。為了解決低壓環境下,電晶體效能不足及嚴重的製程變異影響,本論文使用拔靴帶式電路驅動中繼器,增加小額的功率消耗即可大幅增加傳輸線系統的工作速度。在拔靴帶式電路方面,設計了兩種全新的拔靴帶式電路,解決了傳統拔靴帶式電路所遭遇到的非理想效應,除了改善拔靴帶式電路升降壓的效果之外,更降低了電路在高速工作時所產生的抖動。 本論文使用的製程為UMC90nm,操作電壓為0.2V,資料傳輸率在TT下可達到20Mbps。在TT下操作在20Mbps時,每條傳輸線的功率消耗為57.5nW,單位位元的功率消耗為0.02875pJ / bit,晶片佈局面積為0.743mm2 (958um×776um)。
This thesis proposes an ultra-low power on-chip bus with bootstrapped repeater insertion. The supply voltage is less than the threshold voltage of MOSFET to reduce the power consumption. The poor driving capability of MOSFET and the serious process variation will affect the performance under low-voltage operation environment. For this reason, we employ the bootstrapped repeaters to solve these problems. Although the bootstrapped circuit consumes additional power, the system performance improves greatly. In this thesis, two novel bootstrapped circuits are proposed to solve non-ideal effects in conventional bootstrapped circuits. They not only improve the boosting efficiency, but also reduce the jitter for high-speed operation. The chip is implemented in UMC90nm process, and the supply voltage is 0.2V. At TT corner, the data rate is 20Mbps. The total power is 57.5nW for a channel of 1cm long at 20Mbps. The power consumption per bit is 0.02875(pJ / bit). The chip area is 0.743mm2 (958um×776um).
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079612589
http://hdl.handle.net/11536/41906
Appears in Collections:Thesis


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