標題: 分散式暫存器檔案架構之資料傳輸合成
Communication Synthesis on Distributed Register-File Microarchitecture
作者: 林彥廷
Lin, Yen-Ting
黃俊達
Huang, Juinn-Dar
電子研究所
關鍵字: 合成;分散式暫存器檔案;synthesis;distributed register file
公開日期: 2008
摘要: 進入深次微米時代,過長的連線導致過大的延遲,使得系統的效能難以繼續提高。數種分散式暫存器架構被提出,企圖使用較短的區域連線進行大部分的資料傳輸,以解決延遲的問題。最近,一種名為分散式暫存器檔案的架構被提出,此架構將系統分為數個構造相同的島,而島間連線數目被用作設計早期階段評估系統好壞之指標。這篇論文提出一個合成流程,在分散式暫存器檔案架構上,將島間連線數目減到最少。首先,使用反覆綁定和重新排程之技巧,得到比先前作品更好的結果;接著,資料傳輸被重新規劃,使得島間連線數目能更進一步減少。由實驗結果得知,與前作相比,我們可以將島間連線數目減少達百分之二十四。
In deep-submicron era, global interconnect delay has become the bottleneck while pursuing higher system clock speed. Several distributed register (DR) architectures have been proposed to cope with this problem by keeping most interconnects local. The recently proposed distributed register-file microarchitecture (DRFM) is one of the DR-based architectures. On DRFM, the number of inter-island connections (IICs) is used as an evaluation metric for quality of results in early design phases. This thesis proposes a two-phase resource-constrained communication synthesis algorithm for IIC minimization targeting DRFM. First, an iterative binding-then-rescheduling procedure is used to obtain a better outcome in the expanded solution space. Then, a data detouring procedure is utilized to further minimize the number of IICs. The experimental results show that an average of 24% IIC reduction can be achieved as compared to the previous work.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079611643
http://hdl.handle.net/11536/41769
Appears in Collections:Thesis


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