標題: H.264/AVC可調式視訊解碼器之分析與動作補償設計
Analysis of H.264/AVC Scalable Extension Decoder and Its Motion Compensation Design
作者: 許博淵
Hsu, Po-Yuan
張添烜
Chang, Tian-Sheuan
電子研究所
關鍵字: 可調式視訊編碼;解碼器;動作補償;SVC;Decoder;Motion Compensation
公開日期: 2009
摘要: 可調式視訊編碼,一個新生代的視訊標準,除了繼承H.264的高壓縮率外,還提供了空間、時間、品質三種可調性,使得可調式視訊編碼較原本的H.264複雜許多。本篇論文的主要目標在於針對H.264/AVC可調式視訊解碼器做分析以及實現一個適用於可調式視訊解碼器的動作補償硬體設計。 首先,我們針對可調式視訊解碼器整個系統的記憶體使用作分析,藉由挑選以畫面幀為基礎的解碼流程,系統可以得到最低的內部記憶體使用量和頻寬需求。接著是我們針對可調式視訊解碼器提出的四級管線架構設計,並且提出單次品質層解碼的方法,在同個空間層平行處理基底品質層和品質增強層,使得要處理的巨圖塊在三個品質層的位元流之中可以有66%的縮減。最後則是提出一個高性能的動作補償設計,藉由同個分割區塊資料共用和縮減參考資料等方法,資料頻寬有62-74%的縮減;更進一步,藉由使用兩套內插單元硬體,處理雙向預測區塊的週期數將得以減半。 根據實驗結果,我們提出的動作補償硬體設計的巨圖塊平均處理週期低於160個週期,也低於我們系統限制的227個週期。換句話說,我們所提出的硬體設計可以在135MHz的時脈下,達到每秒處理超過59萬4千個巨圖塊,也就是每秒60張CIF、SD 480p以及HD 1080p的影像。
Scalable Video Coding (SVC), a new generation video codec, not only inherits the high coding efficiency of H.264/AVC standard, but also supports scalabilities of spatial, temporal, and quality domain, inducing SVC much more complicated than H.264/AVC standard. The main goals of this thesis are to perform an analysis of SVC decoder and implement a motion compensation hardware design for it. At first, a memory analysis of SVC decoder system is proposed. By choosing frame-based decoding flow, the system would enjoy the minimum internal memory usage and bandwidth requirement. Then, we propose a four-stage MB-pipeline architecture for our SVC decoder, and there is also a one-pass quality layer decoding method proposed, which parallel processes base quality layer and quality enhancement layers in same spatial domain for 66% reduction of processing MBs in bitstream of three quality layers. Finally, a high performance motion compensation design is presented. By Block Size Based Data Request and Precision Based Data Request, the data bandwidth is reduced by 62-74%. Moreover, by Doubled Hardware of Interpolation Unit scheme, the processing cycles for bi-pred block will be halved. According to experiment results, the average processing cycles in our proposed motion compensation design are below 160 cycles/MB which is under our system constraint 227 cycles/MB. On the other hand, the proposed hardware design can process more than 594k macroblocks per second operating at 135MHz clock rate, which is equivalent to 60 frames of CIF, SD 480p, and HD 1080p resolutions.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079611611
http://hdl.handle.net/11536/41737
Appears in Collections:Thesis


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