標題: 一個可利用在60GHz超寬頻系統的全數位式非整數頻率合成器
An All Digital Fractional Frequency Synthesizer for 60GHz UWB System
作者: 李彥緯
Lee, Yen-Wei
陳巍仁
Chen, Wei-Zen
電子研究所
關鍵字: 全數位式;非整數;頻率合成器;60GHz超寬頻系統;All Digital;Fractional;Fractional;60GHz UWB system
公開日期: 2009
摘要: 摘要 本論文提出一個可用在60GHz 超寬頻系統的40GHz全數位式非整數頻率合成器。其中,在不使用多模除頻器(Multi-Mode Divider)的狀況下,非整數鎖相功能由一個拉回參考相位積分路徑的回授路徑跟和差調變器(Delta-Sigma Modulator)共同組成,利用此機制可產生涵蓋37.5到45.5GHz的頻率範圍。且當輸出頻率為40GHz時,模擬得到的相位雜訊(Phase Noise)值在頻率偏移為1MHz時為-90dBc/Hz。此論文中的晶片是使用90nm CMOS技術實現,整體晶片面積為1.265mm2,核心電路的部份只佔0.594mm2,使用電壓為1.2V,消耗功率約52mW。
Abstract A 40 GHz all digital fractional frequency synthesizer for 60GHz UWB system is presented. Without the helping of a multi-mode divider, the fractional phase locking function is achieved by a feedback around the reference integral path and a delta-sigma modulator. In this mechanism, the locking range covers from 37.5 to 45.5GHz. When the output frequency is 40GHz, the simulated phase noise is -90dBc/Hz at 1MHz frequency offset. Implemented in a 90 nm CMOS technology, the core area is only 0.594 mm2, and the chip size including bonding pad is 1.265mm2. The ADFPLL core consumes 52mW from a 1.2V supply.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079611610
http://hdl.handle.net/11536/41736
Appears in Collections:Thesis


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  1. 161001.pdf
  2. 161002.pdf