標題: 適用於展頻時脈產生器之全數位鎖相迴路
All Digital Phase-Locked Loop for Spread-Spectrum Clock Generator
作者: 蘇明銓
Su, Ming-Chiuan
周世傑
Jou, Shyh-Jye
電子研究所
關鍵字: 數位控制震盪器;全數位鎖相迴路;展頻時脈產生器;Digitally-Controlled Oscillator;All Digital Phase-Locked Loop;Spread-Spectrum Clock Generator
公開日期: 2009
摘要: 摘要 系統晶片中隨著內部參考時脈的提升,為了對抗電磁波干擾的問題,展頻技術被應用在時脈的產生。傳統類比鎖相迴路較易受到製程/電壓/溫度變化的影響。因此在使用深次微米互補式金氧半製程時,鎖相迴路遂逐漸向全數位式設計。 全數位鎖相迴路由bang-bang相位頻率偵測器、使用累加器為主的數位迴路濾波器、差動式數位控制震盪器和除頻器等組成。Bang-bang相位頻率偵測器產生相位比較訊號,控制使用累加器為主的數位迴路濾波器。然後,數位迴路濾波器輸出粗調以及微調的控制碼,用以改變差動式數位控制震盪器的頻率。使用和差調變器進一步控制數位控制震盪器可增加全數位鎖相迴路的頻率解析度。展頻時脈的產生需要應用一個低抖動的全數位鎖相迴路。 展頻技術是對時脈信號的中心頻率做微量的調變,使時脈信號的頻譜展開成較寬的頻帶範圍。因此可降低時脈信號在頻譜上的能量峰值,減少時脈信號所造成的高頻電磁雜訊干擾(Electro-Magnetic Interference, EMI)。未來提出的時脈產生器以全數位鎖相迴路為基本架構,可能使用和差調變器及調變多重相位的方法來實現展頻,並且以符合Serial-ATA 6Gbps的規格和USB 3.0 5Gbps的規格作為參考設計。 展頻時脈產生器可依照系統對低功率需求或是對低抖動需求,選擇以10個輸出相位或是20個輸出相位作展頻。本論文探討全數位鎖相迴路及展頻時脈產生器的設計,以及使用TSMC 65nm 1P9M CMOS製程的模擬。
Abstract As SOC(System On Chip) works with increasing internal reference clocks, the spread-spectrum clocking technique is used to mitigate EMI(Electro-Magnetic Interference) effect. Conventional analog PLLs are likely to be affected by PVT (process/voltage/temperature) variations. Hence, when using deep-submicron CMOS process, PLLs are prone to all-digital design. All-digital PLL consists of bang-bang PFD, accumulator-based digital loop filter, differential DCO and divider. Bang-bang PFD generates phase compare signals to control accumulator-based digital loop filter. Then, DLF outputs coarse-tune and fine-tune control code to change differential DCO’s frequency. Using ΣΔmodulator to further control DCO enhances ADPLL’s frequency resolution. A low-jitter ADPLL is desired under spread-spectrum clocking application. Spread-spectrum technique is to modulate clock’s center frequency, and the spectrum of the clock is spread over a broader range. Therefore, clock’s peak energy is reduced and it also mitigates EMI effect. Based on an ADPLL, the proposed spread spectrum clock generator (SSCG) is fulfilled usingΣΔmodulator and multiple phases. This SSCG uses Serial-ATA 6Gbps and USB 3.0 5Gbps specifications as reference. For different system requirements for low-power or low-jitter, the SSCG can do modulation on 10 or 20 phases. The thesis proposes novel ADPLL and SSCG architecture and the circuits are implemented with TSMC 65nm 1P9M CMOS process.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079611601
http://hdl.handle.net/11536/41728
Appears in Collections:Thesis