標題: 利用新穎結構對P型複晶矽薄膜電晶體進行之熱載子衰退機制分析
A Study of P-Channel Poly-Si TFT Degradation under Hot-Carrier Stress Using a Novel Test Structure
作者: 陳政建
Chan, Cheng-Kin
林鴻志
黃調元
Lin, Horng-Chih
Huang, Tiao-Yuan
電子研究所
關鍵字: 熱載子效應;p型薄膜電晶體;hot carrier effect;p-channel TFTs
公開日期: 2008
摘要: 在本篇論文中,我們利用新穎的測試結構(稱為“熱載子薄膜電晶體”)來對P型複晶矽薄膜電晶體進行熱載子效應的研究。在製程上,它與標準的製程無異,我們不需要增加額外的步驟就能把元件製作出來。此測試結構包含了一組測試電晶體與三組感測電晶體,而此三組感測電晶體分別垂直置放於測試電晶體的通道上。這種設計能有效的偵測出通道在施加偏壓測試後不同區域的受損情況,以及提高區域受損情況之偵測靈敏度。 在研究中,我們分別對P型複晶矽薄膜電晶體進行直流偏壓及交流偏壓的熱載子測試。利用嵌入式的感測電晶體,能夠清楚的觀測出通道中主要的受損區域及陷入閘極氧化層的電子都集中於靠近汲極的位置,而這些結果在傳統的薄膜電晶體中是無法直接感測得出來的。對元件作直流偏壓測試後的結果顯示,當施以閘極直流偏壓大約等於臨界電壓時,元件的受損程度最為嚴重。而在交流偏壓測試中,其頻率、上升時間及下降時間等因素對於元件之影響將進行深入研究與探討。由實驗結果可以證明出,在電壓瞬變的階段會對元件產生額外的損害,而當上升時間或下降時間縮短時,元件會受到更嚴重的額外損害。其可能的受損機制將在本論文中提出。
In this thesis, we investigate the hot-carrier effects of p-channel poly-Si thin film transistors (TFTs) using a novel test structure, called “Hot-Carrier-TFTs” (HC-TFTs). The fabrication of the novel test structure is simple and compatible with standard device manufacturing without additional steps. This test structure includes one test transistor and three monitor transistors, which consist of three source/drain electrode pairs arranged in the direction perpendicular to the normal (i.e., lateral) channel of the test transistor. With such design, it is capable of resolving the damage characteristics in different portions of the stressed channel and greatly enhancing the sensitivity in detecting the localized damage. In this study, both static and dynamic hot-carrier stress tests were applied to the p-channel poly-Si TFTs. Using the embedded monitor transistors, in these tests we can clearly observe major damages, including the trapping of electrons in the gate oxide and defect generation in the poly-Si channel near the drain of the test transistor which is the conventional test structure can not directly sense. For an applied specific drain bias applied during the stress period, the most serious degradation of the test devices occurs under the static stress condition when the gate voltage is close to the threshold voltage. In the dynamic stress test, the effects of input signal factor including frequency, rising time and falling time, were investigated and discussed. The experimental results provide unambiguous evidence that the additional damage occurs during the transient stages, and the device degradation becomes even worse as the rising / falling time is shortened. Possible damage scenarios are proposed to explain the experimental findings.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079611530
http://hdl.handle.net/11536/41664
Appears in Collections:Thesis


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