A Study of P-Channel Poly-Si TFT Degradation under Hot-Carrier Stress Using a Novel Test Structure
|關鍵字:||熱載子效應;p型薄膜電晶體;hot carrier effect;p-channel TFTs|
In this thesis, we investigate the hot-carrier effects of p-channel poly-Si thin film transistors (TFTs) using a novel test structure, called “Hot-Carrier-TFTs” (HC-TFTs). The fabrication of the novel test structure is simple and compatible with standard device manufacturing without additional steps. This test structure includes one test transistor and three monitor transistors, which consist of three source/drain electrode pairs arranged in the direction perpendicular to the normal (i.e., lateral) channel of the test transistor. With such design, it is capable of resolving the damage characteristics in different portions of the stressed channel and greatly enhancing the sensitivity in detecting the localized damage. In this study, both static and dynamic hot-carrier stress tests were applied to the p-channel poly-Si TFTs. Using the embedded monitor transistors, in these tests we can clearly observe major damages, including the trapping of electrons in the gate oxide and defect generation in the poly-Si channel near the drain of the test transistor which is the conventional test structure can not directly sense. For an applied specific drain bias applied during the stress period, the most serious degradation of the test devices occurs under the static stress condition when the gate voltage is close to the threshold voltage. In the dynamic stress test, the effects of input signal factor including frequency, rising time and falling time, were investigated and discussed. The experimental results provide unambiguous evidence that the additional damage occurs during the transient stages, and the device degradation becomes even worse as the rising / falling time is shortened. Possible damage scenarios are proposed to explain the experimental findings.
|Appears in Collections:||Thesis|
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