標題: 低功率迴圈式類比數位資料轉換器
Low Power Cyclic Analog to Digital Data Converter
作者: 歐陽有儀
OuYang, Yu-Yi
陳巍仁
Chen, Wei-Zen
電機學院IC設計產業專班
關鍵字: 迴圈式類比數位轉換器;開路放大器;時序重置;cyclic ADC;open-loop amplifier;timing reschedule
公開日期: 2009
摘要: 本篇論文研製一個應用在0.18微米標準金氧半製程的低功率迴圈式類比數位資料轉換器,可以將輸入端的類比訊號轉換為數位訊號,以利於後級的數位信號處理。 為了達到低功率的要求,在此採用了單級的迴圈式架構,並可增加晶片面積的使用率。其中的運算放大器,可以操作在低功率下,同時達到高增益且不影響暫態的迴轉率(slew rate)。此外,每個循環處理3個位元,再加上時序重置技術(timing re-schedule technique),可以節省後面兩個循環的轉換時間,進而提高速度。本電路可以操作到每秒10個百萬次的資料速度,整體解析度為9個位元。整顆晶片消耗功率約3.6毫瓦。晶片面積是0.21平方毫米。
The thesis presents a solution of the low power cyclic analog to digital data converter which could convert the analog input signal into digital codes for digital signal processing in backend in standard 0.18-□m CMOS technology. Considering the requirement of low power, it adopts the single stage of cyclic scheme, and also improves the efficiency of the chip area. The operational amplifier can achieve low power and high gain without affecting the slew rate in transition behavior simultaneously. Besides, to speed up the conversion rate, there are 3bits in process every cycle, and the timing re-schedule technique is utilized to save more time in the last two cycles. It can operate in 10MHz/s for 9bits resolution. The total power dissipation is 3.6 mW, and the chip size is 0.21 mm2.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079595511
http://hdl.handle.net/11536/41638
Appears in Collections:Thesis


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  1. 551102.pdf