標題: 應用於IEEE 802.11a之10位元100MS/s數位類比轉換器實現
10 Bits 100MS/s Digital to Analog Converter for IEEE 802.11a
作者: 朱陳糧
Liang Chuchen
董蘭榮
Lan-Rong Dung
電機學院電機與控制學程
關鍵字: 數位到類比轉換器;精確度;差動非線性誤差;累積非線性誤差;DAC;Accuracy;differential nonlinearity error DNL;Integral nonlinearity error INL
公開日期: 2005
摘要: 本論文設計實現一個應用於802.11a之10位元100MS/s數位類比轉換器,在數位/類比轉換器電路的實現,切換電流源式是一個很好的實現方法。但由於製程參數漂移的關係,使得數位/類比轉換器的規格很難達到較高的精確度。傳統使用校正電路雖可改善數位/類比轉換器的精確度,但所付出的成本與複雜度也提高許多。故本論文參考一個電流源偏壓技巧,稱為『抗製程漂移偏壓電流源』技術,改善臨界電壓漂移與電源導線壓降造成電流誤差,並應用於電流源的設計,經蒙地卡羅模擬結果證實,利用此方法,受製程參數影響造成Vth 漂移以及(W/L)誤差和電源電壓誤差的影響有顯著的改善。在考量梯度誤差方面電流源採用四象限對稱佈置,消除線性和拋物線梯度誤差。最後使用TSMC 0.35μm Mixed Signal 2P4M製程完成12bit電流源式數位/類比轉換器之設計,完成電路後證實,此一電流源式數位/類比轉換器,有效克服和改善製程漂移,梯度誤差等問題。
This thesis describes a 10-bit 100MS/s digital to analog converter (DAC) for IEEE 802.11a. For high-speed application, The current-source mode has been popular in high speed digital to analog converter applications. However, to obtain accurate current-source is not easy due to process variation. Although several calibration circuits are proposed to improve the accuracy, the cost and circuit complexity are usually very large. In this thesis, based on traditional threshold-voltage compensation method, we use a new current source biasing technique to reduce the current error caused by inevitable threshold-voltage variation, transistor (w/l) size variation, power-source variation and temperature change. Finally we apply this technique to 10-bit weighted-current-source digital to analog converter. SPICE simulations show that for 0.35-μm TSMC Mixed Signal 2P4M process with a 3.3 V power supply; the digital to analog converter variation is reduced significantly.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009067541
http://hdl.handle.net/11536/41247
顯示於類別:畢業論文


文件中的檔案:

  1. 754102.pdf