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dc.contributor.author王泰瑞en_US
dc.contributor.authorWang, Tai-Juien_US
dc.contributor.author郭正次en_US
dc.contributor.author潘扶民en_US
dc.contributor.authorKuo, Cheng-Tzuen_US
dc.contributor.authorPan, Fu-Mingen_US
dc.date.accessioned2014-12-12T01:25:05Z-
dc.date.available2014-12-12T01:25:05Z-
dc.date.issued2010en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079518836en_US
dc.identifier.urihttp://hdl.handle.net/11536/41170-
dc.description.abstract本論文以矽晶圓為基材開發許多不同的金屬輔助奈米閘極堆疊結構,包括: SiO2/Ir-NCs/SiO2/Si-Sub、SiO2/Ir-NCs/Si3N4/SiO2/Si-Sub、SiO2/Ir-silicide- NCs/SiO2/Si-Sub、SiO2/Ir-NCs/SiO2/Si3N4/Poly-Si、SiO2/Ni-NCs/Si3N4/SiO2/Poly-Si、 SiO2/Si3N4/Ni-NCs/Si3N4/SiO2/Poly-Si、SiO2/Si3N4/SiO2/Poly-Si和Al2O3/Si3N4/Ni- NCs/Si3N4/SiO2/Poly-Si 等堆疊結構,並致力於薄膜電晶體非揮發性記憶體元件之應用。其中,所應用到的金屬奈米粒子如: 銥、矽化銥、鎳等奈米粒子,皆採用物理氣相沉積的方式鍍上奈米薄膜再以快速升溫退火或氫電漿處裡的方式製作出奈米粒子。本論文主要的實驗參數包括:三維尺寸分佈的金屬點堆疊層厚度、材料、載子穿隧層工程、預處理的溫度及時間。而其他的堆疊層則是用化學氣相沉積或物理氣相沉積之方式沉積,並將所堆疊完成的結構及元件的各個部位的利用黃光微影製程定義出來。每種堆疊結構和特性皆以掃描式電子顯微鏡 (SEM)、穿透式電子顯微鏡 (TEM)、X射線光電子能譜儀 (XPS)、電容-電壓(C-V)和電流電壓(I-V)測量去分析其結構與性質。 透過比較銥輔助"SiO2/Ir-NCs/SiO2/Si-Sub"和"SiO2/Ir-NCs/Si3N4/SiO2/ Si-Sub"閘極堆疊,其結果顯示使用只有單層氧化矽比氮化矽/氧化矽之雙層非對稱型載子穿隧層的寫入/抹除 (P/E) 效率較低,並且也具有較小的記憶窗(memory window),在+ /-10 V 掃描電壓條件下前者達 8.1 V 而後者高達 12.6 V,並且兩者在經過104秒之後,後者只比前者少5 % 的資料保留力,此外,以 +/-9 V, 100 ms 作耐操度的測試在經過104 週期的條件下並沒有顯著劣化。在雙層的非對稱型結構作用下,電子在寫入操作時,在相同的物理厚度下,相較於只穿隧一個高屏障材料,可藉由穿隧一個高屏障材料和一個低屏障材料,輕易地進入電荷補陷中心。 比較矽化銥"SiO2/Ir-silicide-NCs/SiO2/Si-sub"與銥奈米晶體的閘極堆疊結構,結果顯示前者的堆疊結構有更大的記憶窗(可達14.2 V,於+/-10 V掃描電壓條件),但其資料保留能力比後者降低約 78%。此外,以矽化銥奈米晶體為電荷捕陷中心的閘極堆疊結構,其電荷捕陷密度約為 1.06 × 1013 cm-2,此表示其為一具高捕陷效率的閘極堆疊。 有關於銥奈米晶體躺在氮化矽/氧化矽之不對稱穿隧結構上的薄膜電晶體式非揮發性記憶體 (TFT-NVM)的性能研究,結果顯示,即便比之前討論的堆疊(氮化矽/氧化矽 = 3 nm/3 nm)使用較厚的穿隧層厚度(氮化矽/氧化矽 = 5 nm/5 nm),其仍具有寬大的記憶窗(5.5 V)。此外,104 秒的保留時間之後, 記憶視窗仍可維持達 4.0 V,作為邏輯訊號的辨別以相當足夠。這可能是因為以非對稱穿隧層操作元件所產生的優勢加上銥奈米晶體的密度也以達到文獻中所建議的最佳範圍(在本論文中,銥奈米晶體的密度約 6 x 1011 cm-2,銥奈米晶體直徑約4至12 nm)。 鎳奈米晶體可以成功在450oC下被製造,此製程溫度遠低於一般玻璃基板的耐熱溫度(600oC)並可應用於低溫多晶矽的TFT-NVM。這可能是由於使用氫電漿預處理及使用鎳材料的緣故。此外,鎳奈米晶體密度約為 5 x 1011 cm-2,是已靠近優化的數值。結果還顯示,在 104秒的保留時間後,可以達到約 1.1 V的記憶窗大小,但之所以數值小於上一個堆疊結構,是因為鎳材料具有較小的功函數和此閘極堆疊結構有較薄穿隧層。 透過檢查氮化矽層厚度的影響,結果證明較薄氮化矽厚度(< 5 nm)並且無奈米晶體的堆疊結構,幾乎沒有探測到具有記憶窗。換句話說,薄的氮化矽層幾乎沒有電荷捕獲能力,即可作為一個穿隧層。本實驗的結果還顯示,較厚的氮化矽層(約 15 nm) 可以用來當作具有缺陷密度的電荷捕陷層。在以+/-18 V, 1 s為寫入/抹除條件且無奈米晶體的輔助下,只能獲得約2 V的記憶窗大小,因此,單純以氮化矽層為電荷捕陷層,在操作電壓與記憶窗的大小上必須做出取捨。然而,在閘極堆疊中加入鎳奈米晶體(氧化矽/氮化矽/鎳奈米晶體/氮化矽/氧化矽/多晶矽) 在相同的操作電壓條件下,便能夠進一步增加記憶窗大小達 3.2 V。這是因為除了鎳奈米晶體具有很好的捕陷電荷能力之外,此堆疊結構也產生了很多的異質接面在氮化矽與鎳奈米晶體之間,這些異質接面可能也進一步製造更多的捕陷電荷中心。 將上一組實驗的氧化矽阻絕層(~ 15 nm)更改為很薄的氧化鋁層(~ 5 nm),使得原來電荷從通到注入的操作模式,改由從閘極注入去取代,而其堆疊設計的穿隧機制仍為Fowler-Nordheim機制。結果顯示,由鎳奈米晶體輔助的金屬-氧化鋁-氮化矽-氧化矽-多晶矽之閘極堆疊結構可以大大減少其寫入與抹除的操作電壓,(在-10 V與+ 8 V的操作條件下,記憶窗大小約 4.2 V 歲),並維持可接受的資料保留能力(在經過104 秒後,仍有約1.6 V 的記憶窗大小)。此設計理念主要是透過更改材料以提高電荷穿隧的能力,但不會顯著降低電荷保留能力。總之,本實驗基本上針對於各類奈米晶體輔助的閘極堆疊進行其性能的研究,而形成奈米晶體的製程溫度主要有兩類(< 600oC 或 ~ 900oC),由於兩類的溫差很大不會相互影響,也造就了可製作三維堆疊結構之非揮發性記憶體的優勢。而穿隧和捕陷層工程包括了:非對稱穿隧結構、閘極注入結構、閘極介電材料、金屬材料及厚度,皆可用於設計不同的元件,應用於不同的非揮發性記憶體。zh_TW
dc.description.abstractThis work was to develop various metal-assisted nano-gate stacks on Si wafer, including SiO2/Ir-NCs/SiO2/Si-Sub, SiO2/Ir-NCs/Si3N4/SiO2/Si-Sub, SiO2/Ir-silicide- NCs/SiO2/Si-Sub, SiO2/Ir-NCs/SiO2/Si3N4/Poly-Si, SiO2/Ni-NCs/Si3N4/SiO2/Poly-Si, SiO2/Si3N4/Ni-NCs/Si3N4/SiO2/Poly-Si, SiO2/Si3N4/SiO2/Poly-Si, and Al2O3/Si3N4/ Ni-NCs/Si3N4/SiO2/Poly-Si stack structures. The aims were to use for thin film transistor- nonvolatile memory (TFT-NVM) applications. The metals, including Ir, Ir-silicide, and Ni nano-dots, were deposited by PVD and followed by rapid thermal annealing or hydrogen plasma pretreatments. The other layers of the stacks were deposited by CVD or PVD, and followed by defining device components through lithography processes. The process parameters consist of 3-D size distribution of metallic dots in the stack, layer thickness and material, tunneling layer engineering, pretreatment temperature and time. Each layer structures and stack properties were characterized by scanning electron microscopy (SEM), transmission electron microscopy (TEM), X-ray photoelectron spectroscopy (XPS), capacitance-voltage (C-V) and current-voltage (I-V) measurements. By comparing Ir-assisted “SiO2/ Ir-NCs/ SiO2/ Si-Sub” and “SiO2/Ir-NCs/Si3N4/SiO2/Si-Sub” gate stacks, the results show that performance by tunneling engineering through using asymmetrical Si3N4/SiO2 bi-layer is much better than SiO2 single-layer, in terms of program/erase (P/E) efficiency and memory window size (from 8.1 V up to 12.6 V at +/- 10 V sweeping voltages), with only 5% degrade in data retention and no significant degrade in device endurances up to 104 cycles under P/E stressing condition of +/- 9 V, 100 ms. This is due to the fact that the function of asymmetrical bi-layer is essentially a two-step tunneling action to tunnel electrons into the trapping centers through one high barrier and a slight lower barrier in comparison with one step action through one high barrier under the same total tunneling distance. By comparing Ir-silicide-assisted “SiO2/Ir-silicide-NCs/SiO2/Si-sub” gate stack with Ir-assisted asymmetrical stack, the results have demonstrated that the former stack has a wider memory window (i.e. 14.2 V at sweeps of +/- 10 V can be reached) but less data retention ability (about 78% degrade) than the latter stack. Furthermore, the trap density of the former stack is estimated to be about 1.06×1013 cm-2, indicating a high trapping efficiency stack for nonvolatile memory application. About performance of Ir-NCs-assisted thin film transistor nonvolatile memory (TFT-NVM) devices with Ir-NCs lying on Si3N4/SiO2 asymmetric tunneling layer, the results indicate that a significant memory window of 5.5 V can be obtained even under a thicker tunneling layer thickness (Si3N4/SiO2 = 5 nm/5 nm) than the other previous discussed stacks. Furthermore, after 104 s retention time, the memory window can be maintained up to 4.0 V, which is more than enough to act as logic states. This may take advantages of asymmetric tunneling layer, and the number density of Ir-NCs is within the optimum range as proposed in the literature (in this case, ~ 6 x 1011 cm-2 with particle diameters ranging from 4 to 12 nm). The Ni-NCs can be successfully fabricated under 450oC, which is much lower than temperature tolerance 600oC of glass substrate for low temperature poly-silicon TFT-NVM application. This may be due to applications of H-plasma pretreatment and Ni material for NCs formation. Furthermore, the number density of ~ 5×1011 cm-2 of Ni-NCs is close to the proposed optimum range. The results also indicate that the window size of ~ 1.1 V after 104 s retention time can be reached, which is good enough but less than the values of previous stacks due to a lower work function of Ni material and thinner tunneling layer. By examining thickness effect of Si nitride layer, the results demonstrate that the stacks with thinner nitride thickness (< 5 nm) and without NCs show no detectable window size. In other words, a thinner nitride layer has no significant charge trapping ability, i.e. can act as a tunneling layer. The results also indicate that a thicker nitride layer (about 15 nm) could be used for charge trapping layer due to its great defect density. Therefore, a window size of 2.0 V under a P/E condition of +/- 18 V for 1 sec could be obtained by a trade-off of P/E efficiency. An addition of Ni-NCs in the stack (i.e. SiO2/Si3N4/Ni-NCs/Si3N4/SiO2/Poly-Si) appeals able to further increase window size up to 3.2 V under the same P/E conditions. In addition to good trapping ability of NCs, it may be due to more hetero-interfaces between Ni-NCs/Si3N4 further offering more charge trapping centers. By comparing the following gate stack, effect of changing the blocking layer of the stack to become tunneling layer by replacing thicker SiO2 layer (~ 15 nm) with thinner Al2O3 layer (~ 5 nm) was examined, designing stack with gate injection employing Fowler-Nordheim tunneling mechanism. The results indicate that the Ni-NCs assisted metal-alumina- nitride-oxide-silicon-TFT could greatly reduce the P/E voltages (window size of 4.2 V under -10 V and +8 V), and maintain acceptable data retention ability (memory window of 1.6 V after 104 s). This design idea is essentially to enhance the tunneling ability through changing material without significant reducing the retention ability. In summary, this work examines basically the performance of the stacks with two classes of processing temperature (< 500oC or ~ 900oC), which can be an advantage for fabricating 3-D stack NVM. The tunneling and trapping layer engineering, including asymmetrical structure, gate injection scheme, gate dielectric material, metal-NCs material, and layer thickness, can be used to design different devices for different NVM applications.en_US
dc.language.isoen_USen_US
dc.subject奈米晶體zh_TW
dc.subject非揮發性記憶體zh_TW
dc.subject薄膜電晶體zh_TW
dc.subjectzh_TW
dc.subjectzh_TW
dc.subject矽化銥zh_TW
dc.subjectNanocrystalen_US
dc.subjectNVMen_US
dc.subjectTFTen_US
dc.subjectIridiumen_US
dc.subjectNickelen_US
dc.subjectIr-silicideen_US
dc.title金屬輔助奈米堆疊結構之開發及其在高性能薄膜電晶體非揮發性記憶體元件之應用zh_TW
dc.titleDevelopment of metal-assisted nano-stacks and their applications in high performance TFT-NVMen_US
dc.typeThesisen_US
dc.contributor.department材料科學與工程學系zh_TW
Appears in Collections:Thesis