標題: IEEE 802.16a 分時雙工正交分頻多重進接之下行同步技術研討與在數位訊號處理器上的實現
Study and DSP Implementation of IEEE 802.16a TDD OFDM Downlink Synchronization
作者: 蔣宗書
Tsung-Shu Chiang
林大衛
David W. Lin
電機學院電子與光電學程
關鍵字: 正交分頻多重進接;同步;數位訊號處理器上的實現;802.16a;OFDMA;synchronization;DSP implementation;802.16a
公開日期: 2003
摘要: 在論文中我們介紹一種實現IEEE 802.16a 分時雙工正交分頻多重進接之下行同步技術的方法。下行同步技術包含OFDM 符元(symbol) 開始時間與分數頻率偏移之同步,整數頻率偏移之同步,以及傳送資料訊框(frame)的同步。我們將同步技術以軟體方便實現在Texas Instruments(TI)公司製造型號為TMS320C6416的數位訊號處理器上(DSP)。此處理器的操作平台為Innovative Integration 公司製名為Quixote的cPCI卡。 為了能方便驗証同步技術,我們也同時實現了整個802.16a下行傳輸的系統。為了獲得較高的DSP運算效率,在此系統中所有的運算皆是以定點(fixed-point)的格式來進行。在同步技術中我們以15個位元(bits)代表小數1個位元代表正負號共16位元的定點格式作運算。我們使用了TI提供的程式庫□以組合語言做過最佳化的FFT程式。我們藉著使用C6416本身具有的指令以及將無法做軟體程序規畫(software pipeline scheduling)的迴圈展開(unroll)以達到提高執行效率的目的。在同步技術的程式做過改善之後,其執行效率獲得大幅度的提高。 論文中並針對執行效率做了分析。以軟體實現的同步技術在一顆DSP上執並無法達到即時運算的要求。如果我們要使同步技術的執行可以達到即時運算的要求,我們必須將同步技術分割成數個部份。用更多顆的DSP來實現同步技術或將一部份用FPGA實現。
This thesis presents an implementation method of IEEE 802.16a TDD (time division duplex) OFDMA (frequency-division multiple access) downlink (DL) synchronization techniques. The DL synchronization includes symbol time synchronization, fractional frequency offset synchronization, integer frequency offset synchronization and frame synchronization. Our implementation is software-based, employing Texas Instruments’ TMS320C6416 digital signal processor (DSP) housed on Innovative Integration's Quixote cPCI card. We implement the complete 802.16a DL system to verify the accuracy of synchronization function. The computation on this system is fixed-point for obtaining a higher execution efficiency. The data format we use in synchronization is Q.15 which is a 16 bits fixed-point data format that consists of a sign bit nad 15 fractional bits. We use the assembly-optimized FFT which is supported by TI’s DSP library to obtain the high execution efficiency. We increase the execution efficiency of synchronization by using intrinsics of C6416 DSP and unrolling the disqualified loops to make the software pipeline well scheduled. The efficiency is much increased after we refine the program. The execution efficiency of synchronization is analyzed. We find that the real time operation requirement is over the synchronization execution time. If we want the synchronization function to achieve real-time speed, we must partition the synchronization function into sub-functions and implement these functions either on more DSPs or on FPGA.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009067516
http://hdl.handle.net/11536/41101
Appears in Collections:Thesis


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